MC68331TS datasheet(28/84 Pages) FREESCALE

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MC68331TS/D

NOTES:

1. Operands in parentheses are ignored by the CPU32 during read cycles.

2. Three-byte transfer cases occur only as a result of a long word to byte transfer.

3. The CPU32 does not support misaligned word or long-word transfers.

3.5 Chip Selects

Typical microcontrollers require additional hardware to provide external chip-select signals. Twelve in-

dependently programmable chip selects provide fast two-cycle access to external memory or peripher-

als. Address block sizes of 2 Kbytes to 1 Mbyte can be selected.

Chip-select assertion can be synchronized with bus control signals to provide output enable, read/write

strobes, or interrupt acknowledge signals. Logic can also generate DSACK signals internally. A single

DSACK generator is shared by all circuits. Multiple chip selects assigned to the same address and con-

trol must have the same number of wait states.

Chip selects can also be synchronized with the ECLK signal available on ADDR23.

When a memory access occurs, chip-select logic compares address space type, address, type of ac-

cess, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in

chip-select registers. If all parameters match, the appropriate chip-select signal is asserted. Select sig-

nals are active low. Refer to the following block diagram of a single chip-select circuit.

Table 11 Operand Alignment

Transfer Case

SIZ1

SIZ0

ADDR0

DSACK1

DSACK0

DATA

[15:8]

DATA

[7:0]

Byte to 8-Bit Port (Even/Odd)

OP0

(OP0)

Byte to 16-Bit Port (Even)

OP0

(OP0)

Byte to 16-Bit Port (Odd)

(OP0)

OP0

Word to 8-Bit Port (Aligned)

OP0

(OP1)

Word to 8-Bit Port (Misaligned)3

OP0

(OP0)

Word to 16-Bit Port (Aligned)

OP0

OP1

Word to 16-Bit Port (Misaligned)3

(OP0)

OP0

3 Byte to 8-Bit Port (Aligned)2

OP0

(OP1)

3 Byte to 8-Bit Port (Misaligned)2, 3

OP0

(OP0)

3 Byte to 16-Bit Port (Aligned)2

OP0

OP1

3 Byte to 16-Bit Port (Misaligned)2, 3

(OP0)

OP0

Long Word to 8-Bit Port (Aligned)

OP0

(OP1)

Long Word to 8-Bit Port (Misaligned)3

OP0

(OP0)

Long Word to 16-Bit Port (Aligned)

OP0

OP1

Long Word to 16-Bit Port (Misaligned)3

(OP0)

OP0

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