MC68331TS datasheet(53/84 Pages) FREESCALE

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MC68331TS/D

5.3 QSM Registers

QSM registers are divided into four categories: QSM global registers, QSM pin control registers, QSPI

submodule registers, and SCI submodule registers. The QSPI and SCI registers are defined in separate

sections below. Writes to unimplemented register bits have no meaning or effect, and reads from unim-

plemented bits always return a logic zero value.

The module mapping bit of the SIM configuration register (SIMCR) defines the most significant bit

(ADDR23) of the address, shown in each register figure as Y (Y = $7 or $F). This bit, concatenated with

the rest of the address given, forms the absolute address of each register. Refer to the SIM section of

this technical summary for more information about how the state of MM affects the system.

5.3.1 Global Registers

The QSM global registers contain system parameters used by both the QSPI and the SCI submodules.

These registers contain the bits and fields used to configure the QSM.

The QSMCR contains parameters for the QSM/CPU/intermodule bus (IMB) interface.

STOP — Stop Enable

0 = Normal QSM clock operation

1 = QSM clock operation stopped

STOP places the QSM in a low-power state by disabling the system clock in most parts of the module.

The QSMCR is the only register guaranteed to be readable while STOP is asserted. The QSPI RAM is

not readable. However, writes to RAM or any register are guaranteed to be valid while STOP is assert-

ed. STOP can be negated by the CPU and by reset.

The system software must stop each submodule before asserting STOP to avoid complications at re-

start and to avoid data corruption. The SCI submodule receiver and transmitter should be disabled, and

the operation should be verified for completion before asserting STOP. The QSPI submodule should be

stopped by asserting the HALT bit in SPCR3 and by asserting STOP after the HALTA flag is set.

FRZ1 — Freeze 1

0 = Ignore the FREEZE signal on the IMB

1 = Halt the QSPI (on a transfer boundary)

FRZ1 determines what action is taken by the QSPI when the FREEZE signal of the IMB is asserted.

FREEZE is asserted whenever the CPU enters the background mode.

FRZ0 — Freeze 0

Reserved

Bits [12:8] — Not Implemented

SUPV — Supervisor/Unrestricted

0 = User access

1 = Supervisor access

SUPV defines the assignable QSM registers as either supervisor-only data space or unrestricted data

space.

IARB — Interrupt Arbitration Identification Number

The IARB field is used to arbitrate between simultaneous interrupt requests of the same priority. Each

module that can generate interrupt requests must be assigned a unique, non-zero IARB field value. Re-

fer to 3.8 Interrupts for more information.

QSMCR — QSM Configuration Register

$YFFC00

STOP

FRZ1

FRZ0

SUPV

IARB

RESET:

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