MC68331TS datasheet(45/84 Pages) FREESCALE

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MC68331TS/D

4.3 Status Register

The status register contains the condition codes that reflect the results of a previous operation and can

be used for conditional instruction execution in a program. The lower byte containing the condition

codes is the only portion of the register available at the user privilege level; it is referenced as the con-

dition code register (CCR) in user programs. At the supervisor privilege level, software can access the

full status register, including the interrupt priority mask and additional control bits.

System Byte

T[1:0] —Trace Enable

S —Supervisor/User State

Bits [12:11] —Unimplemented

IP[2:0] —Interrupt Priority Mask

User Byte (Condition Code Register)

Bits [7:5] —Unimplemented

X —Extend

N —Negative

Z —Zero

V —Overflow

C —Carry

4.4 Data Types

Six basic data types are supported:

• Bits

• Packed Binary Coded Decimal Digits

• Byte Integers (8 bits)

• Word Integers (16 bits)

• Long-Word Integers (32 bits)

• Quad-Word Integers (64 bits)

4.5 Addressing Modes

Addressing in the CPU32 is register-oriented. Most instructions allow the results of the specified oper-

ation to be placed either in a register or directly in memory. This flexibility eliminates the need for extra

instructions to store register contents in memory. The CPU32 supports seven basic addressing modes:

• Register direct

• Register indirect

• Register indirect with index

• Program counter indirect with displacement

• Program counter indirect with index

• Absolute

• Immediate

Included in the register indirect addressing modes are the capabilities to post-increment, predecrement,

and offset. The program counter relative mode also has index and offset capabilities. In addition to

these addressing modes, many instructions implicitly specify the use of the status register, stack point-

er, or program counter.

SR —Status Register

RESET:

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