S29GL01GP datasheet(72/81 Pages) SPANSION

72 / 81 page

S29GL-P MirrorBit® Flash Family

S29GL-P_00_A14 October 22, 2012

Da ta

Sh e e t

Table 12.4 S29GL-P Sector Protection Command Definitions, x8

Command (Notes)

Bus Cycles (Notes 1–5)

First/Seventh

Second/Eighth

Third

Fourth

Fifth

Sixth

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Command Set Entry

AAA

555

AAA

Bits Program (6)

XXX

DATA

Read (6)

100

Command Set Exit (7, 8)

XXX

Command Set Entry

AAA

555

AAA

Password Program (9)

XXX

PWA x

PWD x

Password Read (10)

PWD0

PWD 1

PWD 2

PWD 3

PWD 4

PWD 5

PWD 6

PWD 7

Password Unlock (10)

PWD 0

PWD 1

PWD 2

PWD 3

PWD 4

PWD 5

PWD 6

PWD 7

Command Set Exit (7, 8)

XXX

PPB Command Set Entry

AAA

PPB Program (11, 12)2

XXX

All PPB Erase (13)

XXX

PPB Status Read (12)

RD(0)

PPB Command Set Exit (7, 8)

XXX

PPB Lock Command Set Entry

AAA

555

AAA

PPB Lock Bit Set (12)

XXX

PPB Lock Status Read (12)

XXX

RD(0)

PPB Lock Command Set Exit (7, 8)

XXX

DYB Command Set Entry

AAA

555

AAA

DYB Set (11, 12)2

XXX

DYB Clear (12)

XXX

DYB Status Read (12)

RD(0)

DYB Command Set Exit (7, 8)

XXX

Legend

X = Don’t care

RD(0) = Read data.

SA = Sector Address. Address bits Amax–A16 uniquely select any sector.

PWD = Password

PWDx = Password word0, word1, word2, and word3.

Data = Lock Register Contents: PD(0) = Secured Silicon Sector Protection Bit,

PD(1) = Persistent Protection Mode Lock Bit, PD(2) = Password Protection

Mode Lock Bit.

Notes

1. See Table 7.1 on page 19 for description of bus operations.

2. All values are in hexadecimal.

3. All bus cycles are write cycles unless otherwise noted.

4. Data bits DQ15-DQ8 are don’t cares for unlock and command cycles.

5. Address bits AMAX:A16 are don’t cares for unlock and command cycles,

unless SA or PA required. (AMAX is the Highest Address pin.)

6. All Lock Register bits are one-time programmable. Program state = “0” and

the erase state = “1.” The Persistent Protection Mode Lock Bit and the

Password Protection Mode Lock Bit cannot be programmed at the same

time or the Lock Register Bits Program operation aborts and returns the

device to read mode. Lock Register bits that are reserved for future use

default to “1’s.” The Lock Register is shipped out as “FFFF’s” before Lock

7. The Exit command returns the device to reading the array.

8. If any Command Set Entry command was written, an Exit command must

be issued to reset the device into read mode.

9. For PWDx, only one portion of the password can be programmed per each

“A0” command.

10. Note that the password portion can be entered or read in any order as long

as the entire 64-bit password is entered or read.

11. If ACC = VHH, sector protection matches when ACC = VIH.

12. Protected State = “00h,” Unprotected State = “01h.”

13. The All PPB Erase command embeds programming of all PPB bits before

erasure.

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