900844 datasheet(61/118 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

900844

FUNCTIONAL DEVICE OPERATION

POWER SUPPLIES

Figure 26. VNN Efficiency Curve

VNN Status/Control Registers and Bits Description

Reference the register map for read/write conditions and default state for each of these registers

VDDQ

This is a 4.0 MHz fully integrated 2-switch synchronous Buck PWM voltage mode control DC/DC regulator.

The switcher can operate in different modes depending on the load conditions. These modes can be set through the SPI and

include a PFM mode, an Automatic Pulse Skipping mode, and a PWM mode.

VDDQ will be discharged every time the regulator is shutting down.

Table 26. VNN Status and Control Registers Structure and Bits Description

Name

Bits

Description

VNNCNT (ADDR 0x36 - R/W - Default value: 0x04)

CTLVNN

2:0

VNN State Control

x0 = Reserved

x1 = Reserved

x2 = Reserved

x3 = Reserved

x4 = OFF

x5 = PFM

x6 = Automatic Pulse Skipping

x7 = PWM

AOACCTLVNN

5:3

VNN State Control during AOAC Exit (when the Exit pin is EXITSTBY pin is asserted). These bits will be initialized

by the system SPI controller after power up.

X0 = Do not copy

x1 = Do not copy

x2 = Do not copy

x3 = Do not copy

x4 = OFF

x5 = PFM

x6 = Automatic Pulse Skipping

x7 = PWM

Reserved

7:6

Reserved

VNNLATCH (ADDR 0x33 - R/W - Default value: 0x7F)

VIDVNN

6:0

VID VNN Control Through SPI. Signal codes are identical to the VID signal codes. Reference Figure 15 for more

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