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900844 датащи(PDF) 49 Page - Freescale Semiconductor, Inc |
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900844 датащи(HTML) 49 Page - Freescale Semiconductor, Inc |
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49 / 118 page ![]() Analog Integrated Circuit Device Data Freescale Semiconductor 49 900844 FUNCTIONAL DEVICE OPERATION CLOCK GENERATION AND REAL TIME CLOCK (RTC) AIE 5 Alarm Interrupt Enable x0 = Alarm flag (AF) bit in Register C is not permitted to assert the interrupt request flag (IRQF) in Register C x1 = Alarm flag (AF) bit in Register C is permitted to assert the interrupt request flag (IRQF) in Register C Reserved 6 Fixed to 0 SET 7 Set mode enable bit for the program to initialize the time and calendar bytes x0 = The update cycle functions normally by advancing the counts once-per-second. x1 = Any update cycle in progress is aborted and the program may initialize the time and calendar bytes without an update occurring in the midst of initializing. RTCC (ADDR 0x1C - R - Default Value: 0x00) Reserved 3:0 Reserved UF 4 Update-Ended Interrupt Flag. Set after each update cycle. X0 = UIE bit will not effect IRQF state x1 = When UIE bit goes high, the IRQF bit goes high AF 5 Alarm Interrupt Flag. Indicates that the current time has matched the alarm time. X0 = AIE bit will not effect IRQF state x1 = When AIE bit goes high, the IRQF bit goes high Reserved 6 Fixed to 0 IRQF 7 Interrupt Request Flag. IRQF = (AF&AIE) + (UF&UIE) The interrupt request flag (IRQF) is set to a “1” when one or more of the following are true: AF = AIE = “1” UF = UIE = “1” x0 = Above Equation is not true x1 = Above Equation is true RTCD (ADDR 0x1D - R - Default Value: 0x00) Reserved 6:0 Fixed to 000000 VRT 7 The Valid RAM and Time (VRT) bit indicates the condition of the contents of the RTC time and calendar registers. A "0" appears in the VRT bit when the RTC registers have been reset. The processor program should set the VRT bit after the time and calendar are initialized to indicate that the time and calendar are valid. The VRT bit can only be set by reading register D. RTCE (ADDR 0x1E - R/W - Default Value: 0x05) OSCSTP 0 Oscillator (32 kHz) Clock Stop Flag x0 = XTAL Oscillator x1 = Internal RC Oscillator BKDET 1 Coin Cell Backup Voltage Status x0 = No change x1 = Coin Cell below "low-voltage" threshold When this bit is set to 1, the SW takes corresponding action for a coin cell well below the operating voltage, and clears the BKDET to get ready for the next event. POR 2 RTC Reset Flag x0 = No reset was detected x1 = POR occurred SCRATCH 7:3 These bits shall not exert any control over the operation of the RTC, and are intended to be used as scratch pad registers by the system controller. Their contents are erased on RTCPORB. Table 20. RTC Control Registers Structure and Bit Description Name Bits Description |
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