900844 datasheet(48/118 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

900844

FUNCTIONAL DEVICE OPERATION

CLOCK GENERATION AND REAL TIME CLOCK (RTC)

RTCHA (ADDR 0x15 - R/W - Default value: 0x00)

HRSALARM

5:0

Hours Alarm Setting Register

Reserved

Reserved (Fixed to 0)

PA-HA

AM/PM Alarm Setting, Only active during 12 Hr. mode

x0 = AM

x1 = PM

RTCDW (ADDR 0x16 - R/W - Default Value: 0x01)

DOW

2:0

Day of Week counter register: 1= Sunday... 7= Saturday

Reserved

7:3

Reserved

RTCDM (ADDR 0x17 - R/W - Default Value: 0x01)

DOM

5:0

Day Of Month Counter Register

Reserved

7:6

Reserved

RTCM2 (ADDR 0x18 - R/W - Default Value: 0x01)

MONTH

4:0

Months Counter Register

Reserved

6:5

Reserved

19/20

THIS BIT IS NOT SUPPORTED

Always Reads 0 (treated as a reserved bit)

RTCY (ADDR 0x19 - R/W - Default Value: 0x00)

YEAR

7:0

Year Counter Register. Note: Values range from 0 to 99

Table 20. RTC Control Registers Structure and Bit Description

Name

Bits

Description

RTCA (ADDR 0x1A - R - Default Value: 0x20)

Reserved

6:0

Fixed to 010000

UIP

This is the Update In Progress (UIP) bit used as a status flag

x0 = Update cycle not in progress

x1 = Update cycle is in progress or will begin soon

RTCB (ADDR 0x1B - R/W - Default Value: 0x02)

Reserved

Fixed to 0

HRMODE

Hour Format Control

x0 = 12 Hour Mode

x1 = 24 Hour Mode

Data Mode for Time and Calendar Updates

x0 = Binary-Coded-Decimal (BCD)

x1 = Binary

Reserved

Fixed to 0

UIE

Update-Ended Interrupt Enable

x0 = Update-End (UF) bit in Register C is not permitted to assert the interrupt request flag (IRQF) in Register C

x1 = Update-End (UF) bit in Register C is permitted to assert the interrupt request flag (IRQF) in Register C

Table 19. RTC Date/Time Configuration Register Structure and Bits Description

Name

Bits

Description

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