900844 datasheet(47/118 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

900844

FUNCTIONAL DEVICE OPERATION

CLOCK GENERATION AND REAL TIME CLOCK (RTC)

Update-Ended Interrupt

If enabled, an interrupt occurs after every update cycle which indicates that there is over 999 ms available to read valid time

and date information.

RTC Timer Calibration

By default, the calibration circuit is off and clock accuracy is limited to the performance of the 32.768 kHz crystal input. For

clock accuracy beyond the limits of the crystal oscillator, a calibration circuit is included. The processor can use a high-frequency

clock to sample the 32.768 kHz output to determine if it is fast or slow, and calculate an adjustment value. The adjustment

algorithm has a resolution of ±477 nanoseconds-per-second average adjustment, which equates to a time accuracy of

approximately 1.2 seconds per month.

Calibration can be turned on by setting the RTC ADJ bit of the ADJ register. A "0" in the ADJ bit turns calibration off. The Sign

bit in the Trim register determines if periodic adjustments are made to speed up or slow down the clock.

When calibration is enabled, the Trim register is used to grow or shrink the average 1.0 Hz clock period. By default, one second

is defined as 32,768 periods of the CLK32K input pin. Each period of the input clock is approximately 30.5

μs. By occasionally

adding (or subtracting) one extra cycle per second, the average second can be adjusted. If SIGN is high (subtract one),

occasional seconds will be trimmed to 32,767 cycles. If SIGN is low (add one), occasional seconds will be trimmed to 32,769

cycles.

The 6-bit TRIMVAL in the Trim register represents the number of seconds to adjust out of every 64 seconds, and can range

from 0-63. For example, TRIMVAL = 0x08 then 8 seconds out of every 64 will be adjusted up or down, according to the SIGN bit.

CLOCK GENERATION AND REAL TIME CLOCK (RTC) REGISTERS AND BITS DESCRIPTION

Table 19. RTC Date/Time Configuration Register Structure and Bits Description

Name

Bits

Description

RTCS (ADDR 0x10 - R/W - Default Value: 0x00)

SEC

6:0

Seconds Counter Register

Reserved

RTCSA (ADDR 0x11 - R/W - Default Value: 0x00)

SECALARM

6:0

Seconds Alarm Setting Register

Reserved

RTCM1 (ADDR 0x12 -R/W - Default Value: 0x00)

MIN

6:0

Minutes Counter Register

Reserved

RTCMA (ADDR 0x13 - R/W - Default Value: 0x00)

MINALARM

6:0

Minutes Alarm Setting Register

Reserved

RTCH (ADDR 0x14 - R/W - Default Value: 0x00)

HRS

5:0

Hours Counter Register

Reserved

Fixed to 0

PA-H

AM/PM Indication, Only active during 12 Hr. mode

x0 = AM

x1 = PM

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