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900844 датащи(PDF) 39 Page - Freescale Semiconductor, Inc

номер детали 900844
подробное описание детали  Integrated Power Management IC for Ultra-mobile and Embedded Applications
PDF  118 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

900844 датащи(HTML) 39 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
Freescale Semiconductor
39
900844
FUNCTIONAL DEVICE OPERATION
SYSTEM CONTROL INTERFACE
Figure 15. 7-Bit VID Code vs. VCC/VNN Output Voltage
As explained previously, the output voltage setting for the VCC and VNN regulators can be set via the VID/VIDEN pins from
the CPU, or by programming the VNNLATCH and VCCLATCH registers through the SPI interface via the platform controller hub.
Figure 16 shows the relationship between the VID/VIDEN signals, the DVPxVRD bit in the Latch registers, and the VRCOMP
output signal. The figure shows VCC as an example, but is also applicable to VNN
The DVPxVRD bit in the VNNLATCH and VCCLATCH registers controls the select input to the multiplexer. If the DVPxVRD
bit is set to a '0', the regulator uses the VID/VIDEN pins from the CPU, and if the DVPxVRD bit is set to a '1', the regulator uses
the VNNLATCH and VCCLATCH registers to set the output voltage.
When the DVPxVRD bit is set to a '0', any changes to the VNNLATCH and VCCLATCH registers should be ignored. When
the DVPxVRD bit is set to a '1', any changes on the VID/VIDEN pins from the CPU should be ignored.
As soon as the DVPxVRD bit is set to a '1', the regulator switches from using the VID/VIDEN pins to using the VCCLATCH
register, and the output voltage of the regulator changes to what the VCCLATCH register is set.
Figure 16 shows how the PMIC controls the VRCOMP signal. The PMIC toggles the VRCOMP signal any time the DVPxVRD
bit is set to a '1' and the output voltage of the VNN or the VCC regulator changes. If the output voltage of the VCC/VNN regulator
changes and the DVPxVRD bit is set to a '0', the VRCOMP signal should not toggle. VRCOMP only toggles for changes to VCC
and VNN through the SPI registers.
6543210
6 543210
6543210
6 543210
0000000 1.2000 0 100000 1.1000 1000000 0.7000 1 100000 0.3000
0000001 1.2000 0 100001 1.0875 1000001 0.6875 1 100001
OFF
0000010 1.2000 0 100010 1.0750 1000010 0.6750 1 100010
OFF
0000011 1.2000 0 100011 1.0625 1000011 0.6625 1 100011
OFF
0000100 1.2000 0 100100 1.0500 1000100 0.6500 1 100100
OFF
0000101 1.2000 0 100101 1.0375 1000101 0.6375 1 100101
OFF
0000110 1.2000 0 100110 1.0250 1000110 0.6250 1 100110
OFF
0000111 1.2000 0 100111 1.0125 1000111 0.6125 1 100111
OFF
0001000 1.2000 0 101000 1.0000 1001000 0.6000 1 101000
OFF
0001001 1.2000 0 101001 0.9875 1001001 0.5875 1 101001
OFF
0001010 1.2000 0 101010 0.9750 1001010 0.5750 1 101010
OFF
0001011 1.2000 0 101011 0.9625 1001011 0.5625 1 101011
OFF
0001100 1.2000 0 101100 0.9500 1001100 0.5500 1 101100
OFF
0001101 1.2000 0 101101 0.9375 1001101 0.5375 1 101101
OFF
0001110 1.2000 0 101110 0.9250 1001110 0.5250 1 101110
OFF
0001111 1.2000 0 101111 0.9125 1001111 0.5125 1 101111
OFF
0010000 1.2000 0 110000 0.9000 1010000 0.5000 1 110000
OFF
0010001 1.2000 0 110001 0.8875 1010001 0.4875 1 110001
OFF
0010010 1.2000 0 110010 0.8750 1010010 0.4750 1 110010
OFF
0010011 1.2000 0 110011 0.8625 1010011 0.4625 1 110011
OFF
0010100 1.2000 0 110100 0.8500 1010100 0.4500 1 110100
OFF
0010101 1.2000 0 110101 0.8375 1010101 0.4375 1 110101
OFF
0010110 1.2000 0 110110 0.8250 1010110 0.4250 1 110110
OFF
0010111 1.2000 0 110111 0.8125 1010111 0.4125 1 110111
OFF
0011000 1.2000 0 111000 0.8000 1011000 0.4000 1 111000
OFF
0011001 1.1875 0 111001 0.7875 1011001 0.3875 1 111001
OFF
0011010 1.1750 0 111010 0.7750 1011010 0.3750 1 111010
OFF
0011011 1.1625 0 111011 0.7625 1011011 0.3625 1 111011
OFF
0011100 1.1500 0 111100 0.7500 1011100 0.3500 1 111100
OFF
0011101 1.1375 0 111101 0.7375 1011101 0.3375 1 111101
OFF
0011110 1.1250 0 111110 0.7250 1011110 0.3250 1 111110
OFF
0011111 1.1125 0 111111 0.7125 1011111 0.3125 1 111111
OFF
VID
VID (V)
VID
VID (V)
VID
VID (V)
VID
VID (V)



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