PIC32MX795F512LT-80ISLASHPF datasheet(164/256 Pages) MICROCHIP

164 / 256 page

PIC32MX5XX/6XX/7XX

DS61156G-page 164

The processor will exit, or ‘wake-up’, from Sleep on one

of the following events:

• On any interrupt from an enabled source that is

operating in Sleep. The interrupt priority must be

greater than the current CPU priority.

• On any form of device Reset

• On a WDT time-out

If the interrupt priority is lower than or equal to the

current priority, the CPU will remain Halted, but the

PBCLK will start running and the device will enter into

Idle mode.

27.3.2

IDLE MODE

In Idle mode, the CPU is Halted but the System Clock

(SYSCLK) source is still enabled. This allows peripher-

als to continue operation when the CPU is Halted.

Peripherals can be individually configured to Halt when

entering Idle by setting their respective SIDL bit.

Latency, when exiting Idle mode, is very low due to the

CPU oscillator source remaining active.

The device enters Idle mode when the SLPEN bit

(OSCCON<4>) is clear and a WAIT instruction is

executed.

The processor will wake or exit from Idle mode on the

following events:

• On any interrupt event for which the interrupt

source is enabled. The priority of the interrupt

event must be greater than the current priority of

the CPU. If the priority of the interrupt event is

lower than or equal to current priority of the CPU,

the CPU will remain Halted and the device will

remain in Idle mode.

• On any form of device Reset

• On a WDT time-out interrupt

27.3.3

PERIPHERAL BUS SCALING

METHOD

Most of the peripherals on the device are clocked using

the PBCLK. The peripheral bus can be scaled relative to

the SYSCLK to minimize the dynamic power consumed

by the peripherals. The PBCLK divisor is controlled by

PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK to

PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All peripherals

using PBCLK are affected when the divisor is changed.

Peripherals such as USB, interrupt controller, DMA, bus

matrix and prefetch cache are clocked directly from

SYSCLK. As a result, they are not affected by PBCLK

divisor changes.

Changing the PBCLK divisor affects:

• The CPU to peripheral access latency. The CPU

has to wait for next PBCLK edge for a read to

complete. In 1:8 mode, this results in a latency of

one to seven SYSCLKs.

• The power consumption of the peripherals. Power

consumption is directly proportional to the fre-

quency at which the peripherals are clocked. The

greater the divisor, the lower the power consumed

by the peripherals.

To minimize dynamic power, the PB divisor should be

chosen to run the peripherals at the lowest frequency

that provides acceptable system performance. When

selecting a PBCLK divider, peripheral clock require-

ments, such as baud rate accuracy, should be taken

into account. For example, the UART peripheral may

not be able to achieve all baud rate values at some

PBCLK divider depending on the SYSCLK value.

Note 1:

Changing the PBCLK divider ratio

requires recalculation of peripheral tim-

ing. For example, assume the UART is

configured for 9600 baud with a PB clock

ratio of 1:1 and a POSC of 8 MHz. When

the PB clock divisor of 1:2 is used, the

input frequency to the baud clock is cut in

half; therefore, the baud rate is reduced

to 1/2 its former value. Due to numeric

truncation in calculations (such as the

baud rate divisor), the actual baud rate

may be a tiny percentage different than

expected. For this reason, any timing cal-

culation required for a peripheral should

be performed with the new PB clock fre-

quency instead of scaling the previous

value based on a change in the PB divisor

ratio.

Oscillator start-up and PLL lock delays

are applied when switching to a clock

source that was disabled and that uses a

crystal and/or the PLL. For example,

assume the clock source is switched from

POSC to LPRC just prior to entering Sleep

in order to save power. No oscillator start-

up delay would be applied when exiting

Idle. However, when switching back to

POSC, the appropriate PLL and/or

oscillator start-up/lock delays would be

applied.

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