PIC32MX795F512LT-80ISLASHPF datasheet(157/256 Pages) MICROCHIP

157 / 256 page

DS61156G-page 157

PIC32MX5XX/6XX/7XX

24.0 ETHERNET CONTROLLER

The Ethernet controller is a bus master module that

interfaces with an off-chip Physical Layer (PHY) to

implement a complete Ethernet node in a system.

Following are some of the key features of this module:

• Supports 10/100 Mbps data transfer rates

• Supports full-duplex and half-duplex operation

• Supports RMII and MII PHY interface

• Supports MIIM PHY management interface

• Supports both manual and automatic flow control

• RAM descriptor-based DMA operation for both

receive and transmit path

• Fully configurable interrupts

• Configurable receive packet filtering

- CRC check

- 64-byte pattern match

- Broadcast, multicast and unicast packets

- Magic Packet™

- 64-bit hash table

- Runt packet

• Supports packet payload checksum calculation

• Supports various hardware statistics counters

Figure 24-1 illustrates a block diagram of the Ethernet

controller.

FIGURE 24-1:

ETHERNET CONTROLLER BLOCK DIAGRAM

Note 1:

This data sheet summarizes the features

of the PIC32MX5XX/6XX/7XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 35. “Ethernet

Controller”

(DS61155) in the “PIC32

Family Reference Manual”

, which is

available from the Microchip web site

(www.microchip.com/PIC32).

Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization”

this data sheet for device-specific register

and bit information.

TX Bus

Master

RX Bus

Master

TX DMA

TX Flow Control

Host IF

RX DMA

RX Filter

Checksum

MAC

External

PHY

MII/RMII

MIIM

MAC Control

and

Configuration

Registers

TX Function

RX Function

DMA

Control

Registers

Ethernet Controller

RX Flow

Control

Ethernet DMA

RX BM

TX BM

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