PIC32MX795F512LT-80ISLASHPF datasheet(121/256 Pages) MICROCHIP

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DS61156G-page 121

PIC32MX5XX/6XX/7XX

7.0

INTERRUPT CONTROLLER

PIC32MX5XX/6XX/7XX devices generate interrupt

requests in response to interrupt events from peripheral

modules. The interrupt control module exists externally

to the CPU logic and prioritizes the interrupt events

before presenting them to the CPU.

The PIC32MX5XX/6XX/7XX interrupt module includes

the following features:

• Up to 96 interrupt sources

• Up to 64 interrupt vectors

• Single and multi-vector mode operations

• Five external interrupts with edge polarity control

• Interrupt proximity timer

• Module freeze in Debug mode

• Seven user-selectable priority levels for each

vector

• Four user-selectable subpriority levels within each

priority

• Dedicated shadow set for user-selectable priority

level

• Software can generate any interrupt

• User-configurable interrupt vector table location

• User-configurable interrupt vector spacing

A simplified block diagram of the Interrupt Controller

module is illustrated in Figure 7-1.

FIGURE 7-1:

INTERRUPT CONTROLLER MODULE

Note 1: This data sheet summarizes the features

of the PIC32MX5XX/6XX/7XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 8. “Interrupts”

(DS61108)

the

“PIC32

Family

Reference Manual”, which is available

from

the

Microchip

web

site

(www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Interrupt Controller

Vector Number

CPU Core

Priority Level

Shadow Set Number

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