HT68F13 datasheet(39/161 Pages) HOLTEK

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Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to

wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the

instruction following the

²HALT² instruction. If the system is woken up by an interrupt, then two

possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled

but the stack is full, in which case the program will resume execution at the instruction following the

²HALT² instruction. In this situation, the interrupt which woke-up the device will not be immediately

serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack

level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in

which case the regular interrupt response takes place. If an interrupt request flag is set high before

entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled.

ProgrammingConsiderations

If the device is woken up from the SLEEP1 Mode to NORMAL Mode, and the system clock source is

from the HXT oscillator and FSTEN is

²1², the system clock can first be switched to the LIRC

oscillator after wake up.

There are peripheral functions, such as WDT and TMs, for which the fSYS is used. If the system clock

source is switched from fH to fL, the clock source to the peripheral functions mentioned above will

change accordingly.

The on/off condition of fSUB and fS depends upon whether the WDT is enabled or disabled as the WDT

clock source is selected from fSUB.

WatchdogTimer

The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to

unknown locations, due to certain uncontrollable external events such as electrical noise.

WatchdogTimerClockSource

The Watchdog Timer clock source is provided by the internal clock, fS, which is in turn supplied by one

of two sources selected by configuration option: fSUB or fSYS/4. The fSUB clock is sourced from the LIRC

oscillator. The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V.

However, it should be noted that this specified internal clock period can vary with VDD, temperature

and process variations. The other Watchdog Timer clock source option is the fSYS/4 clock. The

Watchdog Timer clock source can originate from the fSUB clock, i.e. its own internal LIRC oscillator or

fSYS/4 determined by a configuration option. The Watchdog Timer source clock is then subdivided by a

ratio of 2

8 to 215 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the

WDTC register.

HT68F13/HT68F14/HT68F15

EnhancedI/OFlashType MCU

Rev.1.10

February9,2011

HT68F13 датащи(PDF) 39 Page - Holtek Semiconductor Inc