HT68F13 datasheet(80/161 Pages) HOLTEK

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Standard Type TM Operating Modes

The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode,

PWM Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating

mode is selected using the TnM1 and TnM0 bits in the TMnC1 register.

Compare Match Output Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively. In

this mode once the counter is enabled and running it can be cleared by three methods. These are a

counter overflow, a compare match from Comparator A and a compare match from Comparator P.

When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a

compare match from Comparator P, the other is when the CCRP bits are all zero which allows the

counter to overflow. Here both TnAF and TnPF interrupt request flags for Comparator A and

Comparator P respectively, will both be generated.

If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare

match occurs from Comparator A. However, here only the TnAF interrupt request flag will be

generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when

TnCCLR is high no TnPF interrupt request flag will be generated. In the Compare Match Output

Mode, the CCRA can not be set to 0.

HT68F13/HT68F14/HT68F15

Enhanced I/O Flash Type MCU

Rev. 1.10

February 9, 2011

Counter Value

0x3FF

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int.

Flag TnPF

CCRA Int.

Flag TnAF

TM O/P Pin

Time

CCRP=0

CCRP > 0

Counter overflow

CCRP > 0

Counter cleared by CCRP value

Pause

Resume

Stop

Counter

Restart

TnCCLR = 0; TnM [1:0] = 00

Output pin set to

initial Level Low

if TnOC=0

Output Toggle with

TnAF flag

Note TnIO [1:0] = 10

Active High Output select

Here TnIO [1:0] = 11

Toggle Output select

Output not affected by TnAF

flag. Remains High until reset

by TnON bit

Output Pin

Reset to Initial value

Output controlled by

other pin-shared function

Output Inverts

when TnPOL is high

Compare Match Output Mode -- TnCCLR = 0

Note:

1. With TnCCLR=0 a Comparator P match will clear the counter

2. The TM output pin is controlled only by the TnAF flag

3. The output pin is reset to itsinitial state by a TnON bit rising edge

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