HT68F13 datasheet(85/161 Pages) HOLTEK

85 / 161 page

However a compare match from Comparator A will also automatically clear the TnON bit and thus

generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the

pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter can

only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In

the Single Pulse Mode CCRP is not used. The TnCCLR and TnDPX bits are not used in this Mode.

Rev. 1.10

February 9, 2011

HT68F13/HT68F14/HT68F15

Enhanced I/O Flash Type MCU

L e a d i n g E d g e

T n O N b i t

0 ® 1

S / W C o m m a n d

S E T " T n O N "

o r

T C K n P i n T r a n s i t i o n

T n O N b i t

1 ® 0

S / W C o m m a n d

C L R " T n O N "

o r

C C R A M a t c h C o m p a r e

P u l s e W i d t h = C C R A V a l u e

T r a i l i n g E d g e

T M n O u t p u t P i n

Single Pulse Generation

Counter Value

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int.

Flag TnPF

CCRA Int.

Flag TnAF

TM O/P Pin

(TnOC=1)

Time

Counter stopped

by CCRA

Pause

Resume

Counter Stops

by software

Counter Reset when

TnON returns high

TnM [1:0] = 10 ; TnIO [1:0] = 11

Pulse Width

set by CCRA

Output Inverts

when TnPOL = 1

No CCRP Interrupts

generated

TM O/P Pin

(TnOC=0)

TCKn pin

Software

Trigger

Cleared by

CCRA match

TCKn pin

Trigger

Auto. set by

TCKn pin

Software

Trigger

Software

Clear

Software

Trigger

Software

Trigger

Single Pulse Mode

Note:

1. Counter stopped by CCRA

2. CCRP is not used

3. The pulse is triggered by the TCKn pin or by setting the TnON bit high

4. A TCKn pin active edge will automatically set the TnON bit high

5. In the Single Pulse Mode, TnIO [1:0] must be set to

²11² and can not be changed.

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