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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HT68F13 датащи(PDF) 98 Page - Holtek Semiconductor Inc |
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HT68F13 датащи(HTML) 98 Page - Holtek Semiconductor Inc |
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98 / 161 page  only be generated on the TPnB output pins. With the TnCCLR bit cleared to zero, the PWM period is set using one of the eight values of the three CCRP bits, in multiples of 128. Now both CCRA and CCRB registers can be used to setup different duty cycle values to provide dual PWM outputs on their relative TPnA and TPnB pins. The TnPWM1 and TnPWM0 bits determine the PWM alignment type, which can be either edge or centre type. In edge alignment, the leading edge of the PWM signals will all be generated concurrently when the counter is reset to zero. With all power currents switching on at the same time, this may give rise to problems in higher power applications. In centre alignment the centre of the PWM active signals will occur sequentially, thus reducing the level of simultaneous power switching currents. Interrupt flags, one for each of the CCRA, CCRB and CCRP, will be generated when a compare match occurs from either the Comparator A, Comparator B or Comparator P. The TnAOC and TnBOC bits in the TMnC1 and TMnC2 register are used to select the required polarity of the PWM waveform while the two TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits pairs are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnAPOL and TnBPOL bit are used to reverse the polarity of the PWM output waveform. · ETM, PWM Mode, Edge-aligned Mode, TnCCLR=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 A Duty CCRA B Duty CCRB If fSYS = 16MHz, TM clock source select fSYS/4, CCRP = 100b, CCRA = 128 and CCRB = 256, The TP1A PWM output frequency = (fSYS/4)/512=fSYS/2048 = 7.8125kHz, duty = 128/512 = 25%. The TP1B_n PWM output frequency = (fSYS/4)/512=fSYS/2048 = 7.8125kHz, duty = 256/512 = 50%. If the Duty value defined by CCRA or CCRB register is equal to or greater than the Period value, then the PWM output duty is 100%. · ETM, PWM Mode, Edge-aligned Mode, TnCCLR=1 CCRA 1 2 3 511 512 1021 1022 1023 Period 1 2 3 511 512 1021 1022 1023 B Duty CCRB · ETM, PWM Mode, Center-aligned Mode, TnCCLR=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 256 512 768 1024 1280 1536 1792 2046 A Duty (CCRA ´2)-1 B Duty (CCRB ´2)-1 · ETM, PWM Mode, Center-aligned Mode, TnCCLR=1 CCRA 1 2 3 511 512 1021 1022 1023 Period 2 4 6 1022 1024 2042 2044 2046 B Duty (CCRB ´2)-1 HT68F13/HT68F14/HT68F15 Enhanced I/O Flash Type MCU Rev. 1.10 98 February 9, 2011 |
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