HT68F13 datasheet(97/161 Pages) HOLTEK

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Timer/Counter Mode

To select this mode, bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1 and TMnC2 register

should all be set high. The Timer/Counter Mode operates in an identical way to the Compare Match

Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the

TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare

Match Output Mode can be used to understand its function. As the TM output pin is not used in this

mode, the pin can be used as a normal I/O pin or other pin-shared function.

PWM Output Mode

To select this mode, the required bit pairs, TnAM1, TnAM0 and TnBM1, TnBM0 should be set to 10

respectively and also the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits should be set to 10 respectively.

The PWM function within the TM is useful for applications which require functions such as motor

control, heating control, illumination control etc. By providing a signal of fixed frequency but of

varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying

equivalent DC RMS values.

As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated

waveform is extremely flexible. In the PWM mode, the TnCCLR bit is used to determine in which way

the PWM period is controlled. With the TnCCLR bit set high, the PWM period can be finely controlled

using the CCRA registers. In this case the CCRB registers are used to set the PWM duty value (for

TPnB output pins). The CCRP bits are not used and TPnA output pin is not used. The PWM output can

Rev. 1.10

February 9, 2011

HT68F13/HT68F14/HT68F15

Enhanced I/O Flash Type MCU

Counter Value

0x3FF

CCRB

CCRA

TnON

TnPAU

TnBPOL

CCRB Int.

Flag TnBF

CCRA Int.

Flag TnAF

TPnB O/P

Time

CCRA=0

CCRA = 0

Counter overflow

CCRA > 0 Counter cleared by CCRA value

Pause

Resume

Stop

Counter Restart

TnCCLR = 1; TnBM [1:0] = 00

Output pin set to

initial Level Low

if TnBOC=0

Output Toggle with

TnBF flag

Note TnBIO [1:0] = 10

Active High Output select

Here TnBIO [1:0] = 11

Toggle Output select

Output not affected by

TnBF flag. Remains High

until reset by TnON bit

Output Pin

Reset to Initial value

Output controlled by

other pin-shared function

Output Inverts

when TnBPOL is high

No TnAF flag

generated on

CCRA overflow

ETM CCRB Compare Match Output Mode -- TnCCLR = 1

Note:

1. With TnCCLR=1 a Comparator A match will clear the counter

2. The TPnB output pin is controlled only by the TnBF flag

3. The TPnB output pin is reset to its initial state by a TnON bit rising edge

4. The TnPF flag is not generated when TnCCLR=1

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