13892 datasheet(92/156 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

13892

FUNCTIONAL DEVICE OPERATION

BATTERY INTERFACE AND CONTROL

POWER DISSIPATION

Since the charge path operates in a linear fashion, the dissipation can be significant and care must be taken to ensure that

the external pass FETs M1 and M2 are not over dissipating when charging. By default, the charge system will protect against

this by a built-in power limitation circuit. This circuit will monitor the voltage drop between CHRGRAW and CHRGISNS, and the

current through the external sense resistor connected between CHRGISNS and BPSNS. When required,.a duty cycle is applied

to the M1 and M2 drivers and thus the charge current, in order to stay within the power budget. At the same time M3 is forced to

conduct to keep the application powered. In case of excessive supply conditions, the power limiter minimum duty cycle may not

be sufficiently small to maintain the actual power dissipation within budget. In that case, the charge path will be disabled and the

CHGFAULTI interrupt generated with the CHGFAULTS[1:0] bits set to 01.

The power budget can be programmed by SPI through the PLIM[1:0] bits. The power dissipation limiter can be disabled by

setting the PLIMDIS bit. In this case, it is advised to use close software control to estimate the dissipated power in the external

pass FETs. The power limiter is automatically disabled in serial path factory mode and in reverse mode.

Since a charger attachment can be a Turn-on event when a product is initially in the Off state, any non-default settings that

are intended for PLIM[1:0] and PLIMDIS, should be programmed early in the configuration sequence, to ensure proper supply

conditions adapted to the application. To avoid any false detection during power up, the power limiter output is blanked at the

start of the charge cycle. As a safety precaution though, the power dissipation is monitored and the desired duty cycle is

estimated. When this estimated duty cycle falls below the power limiter minimum duty cycle, the charger circuit will be disabled.

Table 66. Charger Power Dissipation Limiter Control

00 (default)

600

800

1000

1200

Table 67. Charger Power Dissipation Limiter Characteristics

Power Limiter Accuracy

Up to 2x the power set by PLIM[1:0]

Power Limiter Control Period

500

Power Limiter Blanking Period

Upon charging enabling

1500

Power Limiter Minimum Duty Cycle

REVERSE SUPPLY MODE

The battery voltage can be applied to an external accessory via the charge path, by setting the RVRSMODE bit high. The

current through the accessory supply path is monitored via the charge path sense resistor R2, and can be read out via the ADC.

The accessory supply path is disabled and an interrupt CHGSHORTI is generated when the slow or fast threshold is crossed.

The reverse path is disabled when a current reversal occurs and an interrupt CHREVI is generated.

Table 68. Accessory Supply Main Characteristics

Short-circuit Current Slow Threshold

500

Slow Threshold Debounce Time

1.0

Short-circuit Current Fast Threshold

1840

Fast Threshold Debounce Time

100

μs

Current Reversal Threshold

Current from Accessory

CHGCURR

PLIM[1:0]

Power Limit (mW)

Parameter

Condition

Min

Typ

Max

Units

Parameter

Condition

Min

Typ

Max

Units

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