13892 datasheet(73/156 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

13892

FUNCTIONAL DEVICE OPERATION

SUPPLIES

The Buck switcher topology includes an integrated synchronous rectifier, meaning that the rectifying diode is implemented on

the chip as a low ohmic FET. The placement of an external diode is therefore not required, but overall switcher efficiency may

benefit from this. The buck converters permit a 100% duty cycle operation.

During normal operation, several power modes are possible depending on the loading. For medium and full loading,

synchronous PWM control is the most efficient, while maintaining a constant switching frequency. Two PWM modes are

available: the first mode sacrifices low load efficiency for a continuous switching operation (PWM-NPS). The second mode offers

better low load efficiency by allowing the absence of switching cycles at low output loading (PWM-PS). This pulse skipping

feature improves efficiency by reducing dynamic switching losses by simply switching less often.

In its lowest power mode, the switcher can regulate using hysteresis control known as a Pulse Frequency Modulation (PFM)

control scheme. The frequency spectrum in this case will be a function of input and output voltage, loading, and the external

components. Due to its spectral variance and lighter drive capability, PFM mode is generally reserved for non-active radio modes

and Deep Sleep operation.

Buck modes of operation are programmable for explicitly defined or load-dependent control (Adaptive). Refer to the Buck

Switchers section in Power Control System for details.

Common control bits available to each buck regulator may be designated with a suffix “x” within this specification, where x

stands for 1, 2, 3, or 4 (i.e., SWx = SW1, SW2, SW3, and SW4).

The output voltages of the buck switchers are SPI configurable, and two output ranges are available, individually programmed

with SWxHI for SW2, SW3, and SW4 bucks, SW1 is limited to only one output range. Presets are available for both the Normal

and Standby operation. SW1 and SW2 also include pin controlled DVS operation. When transitioning from one voltage to

another, the output voltage slope is controlled in steps of 25 mV per time step (time step as defined for DVS stepping for SW1

and SW2, fixed at 4.0

μs for SW3 and SW4). This allows for support of dynamic voltage scaling (DVS) by using SPI driven voltage

steps, state machine defined modes, and direct DVSx pin control.

When initially activated, switcher outputs will apply controlled stepping to the programmed value. The soft start feature limits

the inrush current at startup. A built-in current limiter ensures that during normal operation, the maximum current through the coil

is not exceeded. This current limiter can be disabled by setting the SWILIMB bit.

Point of Load feedback is intended for minimizing errors due to board level IR drops.

SWITCHING FREQUENCY

The switchers are driven by a high frequency clock. By default, the PLL generates an effective 3.145728 MHz signal based

upon the 32.768 kHz oscillator signal by multiplying it by 96. To reduce spurious radio channels, the PLL can be programmed

via PLLX[2:0] to different values as shown in Table 44.

Table 44. PLL Multiplication Factor

000

2 752 512

001

2 850 816

010

2 949 120

011

3 047 424

100 (default)

3 145 728

101

3 244 032

110

102

3 342 336

111

105

3 440 640

To reduce overall current drain, the PLL is automatically turned off if all switchers are in a PFM mode or turned off, and if the

PLL clock signal is not needed elsewhere in the system. The clocking system provides nearly instantaneously, a high frequency

clock to the switchers when the switchers are activated or exit the PFM mode for PWM mode. The PLL can be configured for

continuous operation by setting the SPI bit PLLEN = 1.

PLLX[2:0]

Multiplication

Factor

Switching Frequency (Hz)

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