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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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13892 датащи(PDF) 47 Page - Freescale Semiconductor, Inc |
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13892 датащи(HTML) 47 Page - Freescale Semiconductor, Inc |
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47 / 156 page  Analog Integrated Circuit Device Data Freescale Semiconductor 47 13892 FUNCTIONAL DEVICE OPERATION I2C INTERFACE INTERRUPT HANDLING CONTROL The MC13892 has interrupt generation capability to inform the system on important events occurring. An interrupt is signaled to the processor by driving the INT pin high. This is true whether the communication interface is configured for the SPI or I2C. Each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. Each interrupt can be cleared by writing a 1 to the appropriate bit in the Interrupt Status register. This will also cause the interrupt line to go low. If a new interrupt occurs while the processor clears an existing interrupt bit, the interrupt line will remain high. Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high, the interrupt line will not go high. A masked interrupt can still be read from the Interrupt Status register. This gives the processor the option of polling for status from the IC. The IC powers up with all interrupts masked except the USB Low power boot, so the processor must initially poll the device to determine if any interrupts are active. Alternatively, the processor can unmask the interrupt bits of interest. If a masked interrupt bit was already high, the interrupt line will go high after unmasking. The sense registers contain status and input sense bits so the system processor can poll the current state of interrupt sources. They are read only, and not latched or clearable. Interrupts generated by external events are debounced, meaning that the event needs to be stable throughout the debounce period before an interrupt is generated. BIT SUMMARY Table 12 summarizes all interrupt, mask, and sense bits associated with INT control. For more detailed behavioral descriptions, refer to the related chapters. Table 12. Interrupt, Mask and Sense Bits Interrupt Mask Sense Purpose Trigger DebounceTi me Section ADCDONEI ADCDONEM - ADC has finished requested conversions L2H 0 page 99 ADCBISDONEI ADCBISDONEM - ADCBIS has finished requested conversions L2H 0 page 99 TSI TSM - Touch screen wake-up Dual 30ms page 99 CHGDETI CHGDETM CHGDETS CHGENS Charger detection sense is 1 if detected Charger state sense is 1 if active Dual 32 ms 100 ms page 88 USBOVI USBOVM USBOVS VBUS over-voltage Sense is 1 if above threshold Dual 60 μs page 88 CHGREVI CHGREVM - Charger path reverse current L2H 1.0 ms page 88 CHGSHORTI CHGSHORTM - Charger path short circuit L2H 1.0 ms page 88 CHGFAULTI CHGFAULTM CHGFAULTS[1:0] Charger fault detection 00 = Cleared, no fault 01 = Charge source fault 10 = Battery fault 11 = Battery temperature L2H 10 ms page 88 CHGCURRI CHGCURRM CHGCURRS Charge current below threshold Sense is 1 if above threshold H2L 1.0 ms page 88 CCCVI CCCVM CCCVS CCCVI transition detection Dual 100 ms page 88 BPONI BPONM BPONS BP turn on threshold detection. Sense is 1 if above threshold. L2H 30 ms page 55 LOBATLI LOBATLM LOBATLS Low battery detect Sense is 1 if below LOBATL threshold L2H 0 page 55 BVALIDI BVALIDM BVALIDS USB B-session valid Sense is 1 if above threshold Dual L2H: 20- 24 ms H2L: 8- 12 ms page 110 |
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