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13892 датащи(PDF) 69 Page - Freescale Semiconductor, Inc

номер детали 13892
подробное описание детали  Power Management and User Interface IC
PDF  156 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

13892 датащи(HTML) 69 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
Freescale Semiconductor
69
13892
FUNCTIONAL DEVICE OPERATION
OPERATING MODES
Figure 14. Memory Hold Circuit
EXITING FROM LOW POWER OFF MODES
When a Turn On event occurs, any switchers that are active through Low Power Off modes will stay in PFM mode at their
Standby voltage set points until the applicable time slot of the startup sequencer. At that point, the respective switcher is updated
for the PUMSx defined default state for mode and voltage. Subsequent closing of the power gate switches will be coordinated
by software to complete restoration of the full system power tree.
Table 37. Power Gating Characteristics
Output Voltage VOUT
Output High
5.0
5.40
5.70
V
Output Low
-
-
100
mV
Turn-on Time (54), (55)
Enable to VOUT = VOUTMIN -250 mV
-
50
100
μs
Turn Off Time
Disable to VOUT < 1.0 V
-
-
1
μs
Average Bias Current
t > 500
μs after Enable
-
1.0
5
μA
PWGTx Input Voltage
NMOS drain voltage
0.6
-
2.0
V
DC Load Current
At PWGTDRVx output
-
-
100
nA
Load Capacitance (54)
Used as a condition for the other parameters
0.5
-
1.0
nF
Notes
54.
Larger capacitive loading values will lead to longer turn on times exceeding the given limits; smaller values will lead to larger ripple at
the output.
55.
Input supply is assumed in the range of 3.0 < BP < 4.65 V; lower BP values may extend turn on time, and functionality not supported
for BP less than ~2.7 V.
POWER GATING SPECIFICATIONS AND CONTROL
A power gate driver pulled low may be thought of as power gating being active since this is the condition where a power source
is isolated (or power gated) from its loading on the other side of the switch. The power gate drive outputs are SPI controlled in
the active modes as shown in Table 38.
Table 38. Power Gate Drive State Control
Off
L
ow
Low
Cold Start
Low
Low
Warm Start
Low
Low
Watchdog, On, User Off Wait
SPI Controlled
SPI Controlled
User Off, Memory Hold, Internal Memory Hold Power Cut
Low
Low
Parameter
Condition
Min
Typ
Max
Units
Mode
PWGTDRV1
PWGTDRV2



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