13892 datasheet(80/156 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

13892

FUNCTIONAL DEVICE OPERATION

SUPPLIES

When configured for SID mode, a high pulse on the DVSx pin will indicate one of 3 actions to take, with the decoding as a

function of how many contiguous SPI clock falling edges are seen while the DVSx pin is held high.

Table 51. SID Control Protocol

No action. Switcher stays at its presently programmed configuration

Jog down. Drive buck switcher output down a single DVS step

Jog up. Drive buck switcher output up a single DVS step

3 or more

Panic Mode. DVS step the buck switcher output to the Normal mode value as programmed in the SPI register

The SID protocol is illustrated by way of example, assuming SIDEN = 1, and that DVS1 is controlling SW1. SW1 starts out at

its default value of 1.250 V (SW1 = 11010) and is stepped both up and down via the DVS1 pin. The SPI bits SW1 = 11010 do

not change. The set point adjustment takes place in the SID block prior to bit delivery to the switcher's digital control.

SW1 output

DVS1

SPICLK

Down

1.250

1.275

1.250

Down

1.225

Starting Value

DVS

Down

DVS

Down

SPICLK shut down

when not used

Figure 21. SID Control Example for Increment & Decrement

SID Panic Mode is provided for rapid recovery to the programmed Normal mode output voltage, so the processor can quickly

recover to its high performance capability with a minimum of communication latency. In Figure 22, Panic Mode recovery is

illustrated as an Increment step, initiated by the detection of the second falling SPI clock edge, followed by a continuation to the

programmed SW1[4:0] level (1.250 V in this example), due to the detection of the third contiguous falling edge of SPI clock while

DVS1 is held high.

SW1 output

DVS1

SPICLK

1.050

Starting Value

DVS

SID Panic Mode Example

Panic

DVS step all the way back to 1.250V

(SW1[4:0] programmed value = 1.250V)

SPICLK shut down when not used

Figure 22. SID Control Example for Panic Mode Recovery

The system will not respond to a new jog command until it has completed a DVS step that may be in progress. Any missed

jog requests will not be stored. For instance, if a switcher is stepping up in voltage with a 25 mV step over a 4.0

μs time, response

to the DVSx pin for another step will be ignored until the DVS step period has expired. However, the Panic Mode step recovery

should respond immediately upon detection of the third SPICLK edge while the corresponding DVSx pin is high, even if the initial

decode of the jog up command is ignored, because it came in before the previous step was completed.

Number of SPI CLK Falling

Edges while DVSx = 1

Function

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