13892 datasheet(41/156 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

13892

FUNCTIONAL DEVICE OPERATION

PROGRAMMABILITY

FUNCTIONAL DEVICE OPERATION

PROGRAMMABILITY

INTERFACING OVERVIEW AND CONFIGURATION OPTIONS

The 13892 contains a number of programmable registers for control and communication. The majority of registers are

accessed through a SPI interface in a typical application. The same register set may alternatively be accessed with an I2C

interface that is muxed on SPI pins. The following table describes the muxed pin options for the SPI and I2C interfaces. Further

details for each interface mode follow in this chapter.

Table 7. SPI / I2C Bus Configuration

Configuration (31), Chip Select

Configuration (32)

CLK

SPI Clock

SCL: I2C bus clock

MISO

Master In, Slave Out (data output)

SDA: Bi-directional serial data line

MOSI

Master Out, Slave In (data input)

A0 Address Selection (33)

Notes

31.

CS held low at Cold Start configures interface for SPI mode; once activated, CS functions as the SPI Chip Select.

32.

CS tied to VCORE at Cold Start configures interface for I2C mode; the pin is not used in I2C mode other than for configuration.

33.

In I2C mode, the MOSI pin hardwired to ground or VCORE is used to select between two possible addresses.

SPI INTERFACE

The 13892 contains a SPI interface port, which allows access by a processor to the register set. Via these registers, the

resources of the IC can be controlled. The registers also provide status information about how the IC is operating, as well as

information on external signals.

The SPI interface pins can be reconfigured for reuse as an I2C interface. As a result, a configuration protocol mandates that

the CS pin is held low during a turn on event for the IC (a weak pull-down is integrated on the CS pin. With the CS pin held low

during startup (as would be the case if connected to the CS driver of an unpowered processor, due to the integrated pull-down),

the bus configuration will be latched for SPI mode.

The SPI port utilizes 32-bit serial data words comprised of 1 write/read_b bit, 6 address bits, 1 null bit, and 24 data bits. The

addressable register map spans 64 registers of 24 data bits each.

The general structure of the register set is given in the following table. Bit names, positions, and basic descriptions are

provided in SPI Bitmap. Expanded bit descriptions are included in the following functional chapters for application guidance. For

brevity's sake, references are occasionally made herein to the register set as the “SPI map” or “SPI bits”, but note that bit access

is also possible through the I2C interface option, so such references are implied as generically applicable to the register set

accessible by either interface.

Pin Name

SPI Mode Functionality

I2C Mode Functionality

Table 8. Register Set

Interrupt Status 0

Unused

Regulator Mode 0

Charger 0

Interrupt Mask 0

Unused

Regulator Mode 1

USB0

Interrupt Sense 0

Memory A

Power Miscellaneous

Charger USB1

Interrupt Status 1

Memory B

Unused

LED Control 0

Interrupt Mask 1

RTC Time

Unused

LED Control 1

Interrupt Sense 1

RTC Alarm

Unused

LED Control 2

Power Up Mode Sense

RTC Day

Unused

LED Control 3

Identification

RTC Day Alarm

Unused

Switchers 0

Unused

ACC 0

Switchers 1

Unused

Trim 0

ACC 1

Switchers 2

Unused

Trim 1

Unused

Switchers 3

ADC 0

Test 0

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