13892 datasheet(65/156 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

13892

FUNCTIONAL DEVICE OPERATION

OPERATING MODES

POWER SAVING

SYSTEM STANDBY

A product may be designed to go into DSM after periods of inactivity, such as if a music player completes a play list and no

further activity is detected, or if a gaming interface sits idle for an extended period. Two Standby pins are provided for board level

control of timing in and out of such deep sleep modes.

When a product is in DSM it may be able to reduce the overall platform current by lowering the switcher output voltage,

disabling some regulators, or forcing some GPO low. This can be obtained by SPI configuration of the Standby response of the

circuits along with control of the Standby pins.

To ensure that shared resources are properly powered when required, the system will only be allowed into Standby when both

the STANDBY and the STANDBYSEC are activated. The states of the Standby pins only have influence in On mode. A command

to transition to one of the Low Power Off states (User Off or Memory Hold, initiated with USEROFFSPI = 1) has priority over

Standby.

Note that the Standby pins are programmable for Active High or Active Low polarity, and that decoding of a Standby event will

take into account the programmed input polarities associated with each pin.

Table 30. Standby Pin and Polarity Control

Notes

46.

STANDBY = 0: System is not in Standby; STANDBY = 1: System is in Standby and Standby programmability is activated.

When requesting standby, a programmable delay (STBYDLY) of 0 to 3 clock cycles of the 32 kHz clock is applied before

actually going into standby (i.e. before turning off some supplies). No delay is applied when coming out of standby.

Table 31. Delay of STANDBY- Initiated Response

No Delay

One 32 K period (default)

Two 32 K periods

Three 32 K periods

REGULATOR MODE CONTROL

The regulators with embedded pass devices (VDIG, VPLL, VIOHI, VUSB, VUSB2, and VAUDIO) have an adaptive biasing

scheme, thus, there are no distinct operating modes such as a Normal mode and a Low Power mode. Therefore, no specific

control is required to put these regulators in a Low Power mode.

The regulators with external pass devices (VSD, VVIDEO, VGEN1, and VGEN2) can also operate in a Normal and Low Power

mode. However, since a load current detection cannot be performed for these regulators, the transition between both modes is

not automatic and is controlled by setting the corresponding mode bits for the operational behavior desired.

The regulators VGEN3 and VCAM can be configured for using the internal pass device or external pass device as explained

in Power Control System. For both configurations, the transition between Normal and Low Power modes is controlled by setting

the VxMODE bit for the specific regulator. Therefore, depending on the configuration selected, the automatic Low Power mode

is available.

The regulators can be disabled and the general purpose outputs can be forced low when going into Standby as described

previously. Each regulator and GPO has an associated SPI bit for this. When the bit is not set, STANDBY is of no influence. The

actual operating mode of the regulators as a function of STANDBY is not reflected through the SPI. In other words, the SPI will

read back what is programmed, not the actual state.

STANDBY (Pin)

STANDBYINV (SPI bit)

STANDBYSEC (Pin)

STANDBYSECINV (SPI bit)

STANDBY Control (46)

STBYDLY[1:0]

Function (1)

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