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13892 датащи(PDF) 42 Page - Freescale Semiconductor, Inc |
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13892 датащи(HTML) 42 Page - Freescale Semiconductor, Inc |
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42 / 156 page ![]() Analog Integrated Circuit Device Data 42 Freescale Semiconductor 13892 FUNCTIONAL DEVICE OPERATION PROGRAMMABILITY The SPI interface is comprised of the package pins listed in Table 9. Table 9. SPI Interface Pin Description CLK Clock input line, data shifting occurs at the rising edge MOSI Serial data input line MISO Serial data output line CS Clock enable line, active high INT Interrupt to processor SPIVCC Processor SPI bus supply SPI INTERFACE DESCRIPTION The control bits are organized into 64 fields. Each of these 64 fields contains 32 bits. A maximum of 24 data bits are used per field. In addition, there is one “dead” bit between the data and address fields. The remaining bits include 6 address bits to address the 64 data fields and one write enable bit to select whether the SPI transaction is a read or a write. The register set will be to a large extent compatible with the MC13783 in order to facilitate software development. For each SPI transfer, first a one is written to the read/write bit if this SPI transfer is to be a write. A zero is written to the read/ write bit if this is to be a read command only. The CS line must remain high during the entire SPI transfer. To start a new SPI transfer, the CS line must go inactive and then go active again. The MISO line will be tri-stated while CS is low. To read a field of data, the MISO pin will output the data field pointed to by the 6 address bits loaded at the beginning of the SPI sequence. Figure 5. SPI Transfer Protocol Single Read/Write Access 12 Unused 28 Switchers 4 44 ADC 1 60 Test 1 13 Power Control 0 29 Switchers 5 45 ADC 2 61 Test 2 14 Power Control 1 30 Regulator Setting 0 46 ADC 3 62 Test 3 15 Power Control 2 31 Regulator Setting 1 47 ADC4 63 Test 4 SPI Bus Description Interrupt Description Supply Description Table 8. Register Set Register Register Register Register |
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