L9803 datasheet(100/126 Pages) STMICROELECTRONICS

100 / 126 page

On-Chip Peripherals

L9803

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The following table summarizes the driving mode selection made by PWM_EN, IN1 and IN2

bit

Bit 4= DIR: Direction bit. This bit is meaningless when PWM_EN=0. When PWM_EN is set

the DIR bit controls the “driving direction” of the bridge. In order to implement a precise

control of the direction changes, DIR value is latched by the rising edge of the pwm signal

driving the bridge. When the signal does not have edges (i.e. pwm = 0% or 100%) the DIR

bit can not be latched and the driving direction does not change even changing DIR bit in

BCSR.

Bit 5= SC: Short Circuit flag (read only)

Bit 6= OVT: Overtemperature flag (read only)

Bit 7= PIE: Power section interrupt enable.

5.9

EEPROM (EEP)

5.9.1

Introduction

The Electrically Erasable Programmable Read Only Memory is used to store data that need

a non volatile back-up. The use of the EEPROM requires a basic protocol described in this

chapter.

Software or hardware reset and halt modes are managed immediately, stopping the action

in progress. Wait mode does not affect the programming of the EEPROM.

The Read operation of this memory is the same of a Read-Only-Memory or RAM. The erase

and programming cycles are controlled by an EEPROM control register.

The user can program 1 to 4 bytes at the same programming cycle providing that the high

part of the address is the same for the bytes to be written (only address bits A1 and A0 can

change).

The EEPROM is mono-voltage. A charge pump generates the high voltage internally to

enable the erase and programming cycles. The erase and programming cycles are chained

automatically. The global programming cycle duration is controlled by an internal circuit.

PWM_EN

IN1

IN2

Driving Mode

Direct

PWM1 Up Braking

PWM1 Down Braking

PWM1 Symmetrical

PWM1/PWM2

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