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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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L9803 датащи(PDF) 78 Page - STMicroelectronics |
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L9803 датащи(HTML) 78 Page - STMicroelectronics |
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78 / 126 page  On-Chip Peripherals L9803 78/126 RUN bit being read-back as 0. Once in standby, the only event monitored is the reception of a dominant bit which causes a wake-up interrupt if the SCIE bit of the Interrupt Control Register (ICR) is set. The STANDBY mode is left by setting the RUN bit. If the WKPS bit is set in the CSR register, then the controller passes through WAKE-UP otherwise it enters RESYNC directly. It is important to note that the wake-up mechanism is software-driven and therefore carries a significant time overhead. All messages received after the wake-up bit and before the controller is set to run and has completed synchronization are ignored. ● WAKE-UP. The CAN bus line is forced to dominant for one bit time signalling the wake- up condition to all other bus members. Figure 39. CAN Controller State Diagram n ● RESYNC. The resynchronization mode is used to find the correct entry point for starting transmission or reception after the node has gone asynchronous either by going into the STANDBY or bus-off states. Resynchronization is achieved when 128 sequences of 11 recessive bits have been STANDBY RESYNC WAKE-UP RECEPTION TRANSMISSION ERROR IDLE ARESET RUN RUN & WKPS RUN & WKPS FSYN & BOFF & 11 Recessive bits | (FSYN | BOFF) & 128 * 11 Recessive bits RUN Write to DATA7 | TX Error & NRTX Start Of Frame Arbitration lost TX Error RX Error TX OK RX OK BOFF BOFF |
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