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L9803 датащи(PDF) 54 Page - STMicroelectronics

номер детали L9803
подробное описание детали  Super smart power motor driver with 8-Bit MCU, RAM, EEPROM, ADC, WDG, Timers, PWM and H-bridge driver
PDF  126 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L9803 датащи(HTML) 54 Page - STMicroelectronics

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On-Chip Peripherals
L9803
54/126
Bit 7 = ICIE Input Capture Interrupt Enable.
0:
Interrupt is inhibited.
1:
A timer interrupt is generated whenever the ICF1 or ICF2 bits of the SR register are set
Bit 6 = OCIE Output Compare Interrupt Enable.
0:
Interrupt is inhibited.
1:
A timer interrupt is generated whenever the OCF1 or OCF2 bits of the SR register are
set
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0:
Interrupt is inhibited.
1:
A timer interrupt is enabled whenever the TOF bit of the SR register is set.
Bit 4 = FOLV2 Forced Output Compare 2.
0:
No effect.
1:
Forces the OLVL2 bit to be copied to the OCMP2 pin.
Bit 3 = FOLV1 Forced Output Compare 1.
0:
No effect.
1:
Forces OLVL1 to be copied to the OCMP1 pin.
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the
OCR2 register. This value is copied to the OCMP1 pin in One Pulse Mode and Pulse Width
Modulation mode.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition on the ICAP1 pin will trigger the capture.
0:
A falling edge triggers the capture.
1:
A rising edge triggers the capture.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with
the OCR1 register.
CONTROL REGISTER 2 (CR2)
Timer1 Register Address: 0031h
Timer2 Register Address: 0041h



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