L9803 datasheet(82/126 Pages) STMICROELECTRONICS

82 / 126 page

On-Chip Peripherals

L9803

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(ETX = 1).

Cleared by software.

Bit 3 = SCIF Status Change Interrupt Flag

− Read/Clear

Set by hardware to signal the reception of a dominant bit while in standby or a change from

error active to error passive and bus-off while in run. Also signals any receive error when

ESCI = 1.

Cleared by software.

Bit 2 = ORIF Overrun Interrupt Flag

− Read/Clear

Set by hardware to signal that a message could not be stored because no receive buffer

was available.

Cleared by software.

Bit 1 = TEIF Transmit Error Interrupt Flag

− Read/Clear

Set by hardware to signal that an error occurred during the transmission of the highest

priority message queued for transmission.

Cleared by software.

Bit 0 = EPND Error Interrupt Pending

− Read Only

Set by hardware when at least one of the three error interrupt flags SCIF, ORIF or TEIF is

set.

Reset by hardware when all error interrupt flags have been cleared.

Caution:

Interrupt flags are reset by writing a "0" to the corresponding bit position. The appropriate

way consists in writing an immediate mask or the one’s complement of the register content

initially read by the interrupt handler. Bit manipulation instruction BRES should never be

used due to its read-modify-write nature.

INTERRUPT CONTROL REGISTER (ICR)

Read/Write

Reset Value: 00h

Bit 6 = ESCI Extended Status Change Interrupt

− Read/Set/Clear

Set by software to specify that SCIF is to be set on receive errors also.

Cleared by software to set SCIF only on status changes and wake-up but not on all receive

errors.

Bit 5 = RXIE Receive Interrupt Enable

− Read/Set/Clear

Set by software to enable an interrupt request whenever a message has been received free

of errors.

Cleared by software to disable receive interrupt requests.

ESCI

RXIE

TXIE

SCIE

ORIE

TEIE

ETX

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