L9803 datasheet(79/126 Pages) STMICROELECTRONICS

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L9803

On-Chip Peripherals

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monitored unless the node is not bus-off and the FSYN bit in the CSR register is set in

which case a single sequence of 11 recessive bits needs to be monitored.

●

IDLE. The CAN controller looks for one of the following events: the RUN bit is reset, a

Start Of Frame appears on the CAN bus or the DATA7 register of the currently active

page is written to.

●

TRANSMISSION. Once the LOCK bit of a Buffer Control/Status Register (BCSRx) has

been set and read back as such, a transmit job can be submitted by writing to the

DATA7 register. The message with the highest priority will be transmitted as soon as

the CAN bus becomes idle. Among those messages with a pending transmission

request, the highest priority is given to Buffer 3 then 2 and 1. If the transmission fails

due to a lost arbitration or to an error while the NRTX bit of the CSR register is reset,

then a new transmission attempt is performed . This goes on until the transmission

ends successfully or until the job is cancelled by unlocking the buffer, by setting the

NRTX bit or if the node ever enters bus-off or if a higher priority message becomes

pending. The RDY bit in the BCSRx register, which was set since the job was

submitted, gets reset. When a transmission is in progress, the BUSY bit in the BCSRx

(ISR) is set, else the TEIF bit is set. An interrupt is generated in either case provided

the TXIE and TEIE bits of the ICR register are set. The ETX bit in the same register is

used to get an early transmit interrupt and to automatically unlock the transmitting

buffer upon successful completion of its job. This enables the CPU to get a new

transmit job pending by the end of the current transmission while always leaving two

buffers available for reception. An uninterrupted stream of messages may be

transmitted in this way at no overrun risk.

Note 1: Setting the SRTE bit of the CSR register allows transmitted messages to be

simultaneously received when they pass the acceptance filtering. This is particularly

useful for checking the integrity of the communication path.

Note 2: When the ETX bit is reset, the buffer with the highest priority and with a

pending transmission request is always transmitted. When the ETX bit is set, once a

buffer participates in the arbitration phase, it is sent until it wins the arbitration even if

another transmission is requested from a buffer with a higher priority.

●

RECEPTION. Once the CAN controller has synchronized itself onto the bus activity, it

is ready for reception of new messages. Every incoming message gets its identifier

compared to the acceptance filters. If the bitwise comparison of the selected bits ends

up with a match for at least one of the filters then that message is elected for reception

and a target buffer is searched for. This buffer will be the first one - order is 1 to 3 - that

has the LOCK and RDY bits of its BCSRx register reset.

–

When no such buffer exists then an overrun interrupt is generated if the ORIE bit

of the ICR register has been set. In this case the identifier of the last message is

made available in the Last Identifier Register (LIDHR and LIDLR) at least until it

gets overwritten by a new identifier picked-up from the bus.

–

When a buffer does exist, the accepted message gets written into it, the ACC bit in

the BCSRx register gets the number of the matching filter, the RDY and RXIF bits

get set and an interrupt is generated if the RXIE bit in the ISR register is set.

Up to three messages can be automatically received without intervention from the CPU

because each buffer has its own set of status bits, greatly reducing the reactiveness

requirements in the processing of the receive interrupts.

●

ERROR. The error management as described in the CAN protocol is completely

handled by hardware using 2 error counters which get incremented or decremented

according to the error condition. Both of them may be read by the application to

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