L9803 datasheet(67/126 Pages) STMICROELECTRONICS

номер детали	L9803

подробное описание детали	Super smart power motor driver with 8-Bit MCU, RAM, EEPROM, ADC, WDG, Timers, PWM and H-bridge driver

PDF	126 Pages

Scroll/Zoom	100%

производитель	STMICROELECTRONICS [STMicroelectronics]

домашняя страница	http://www.st.com

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L9803

On-Chip Peripherals

67/126

5.4

PWM I/O

5.4.1

Introduction

The PWM I/O interface is a circuit able to connect internal logic circuits with external high

voltage lines.

The two interfaces represent respectively the receiver and the transmitter section of a

standard IS0 9141 transceiver.

Connecting PWMO and PWMI together a standard K bus (ISO 9141) can be realized.

Voltage thresholds are referred to the battery voltage connected to VBR pin. This pin must

be used as reference for the K bus. Voltage drops between this pin and the battery line can

cause thresholds mismatch between the L9803 ISO trasceiver and the counterpart

trasceiver(s) connected to the same bus line.

See Figure 32 for a block diagram description of the two interfaces.

Figure 32.

PWM I/O Block Diagram

5.4.2

PWMO

PWMO is an output line, directly driven by the PWM2 output signal. The circuit translates

the logic levels of PWM2 output to voltage levels referred to the VB supply (see Figure 32).

When PWM2=0 the open drain is switched off, in the other case the PWMO line is pulled

down by the open drain driver.

PWMO is protected against short circuit to battery by a dedicated circuit that limits the

current sunk by the output transistor. When the limiter is activated the voltage on PWMO pin

rises up. If the limiter remains active for more than 25µs the driver is switched off.

If the battery or ground connection are lost, the PWMO line shows a controlled impedance

characteristic (see Figure 33).

PWM0 is high at NRESET is asserted.

VDD

PWMO

VDD

TIMER CAPTURE INPUT

PWM2 OUTPUT

PB2 REGISTER BIT

PWMI

VBR

Battery

K bus

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