CDCE72010RGCT datasheet(27/73 Pages) TI

27 / 73 page

CDCE72010

www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009

SPI

RAM

POWER UP

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

BIT

CONDITION

Address 0

Address 1

Address 2

Address 3

0 Feedback Frequency Detector is connected to the Lock Detector

FB_FD_DESEL

1 Feedback Frequency Detector is disconnected from the Lock Detector

LOCK-DET

EEPROM

RESERVED

Set to 0

0 FB-Deterministic Clock divided by 1

FBDETERM_DIV_SEL

1 FB- Deterministic Clock divided by 2

FB-

0 FB-Deterministic-DIV2-Block in normal operation

FBDETERM_DIV2_DIS

Divider/Deterministi

EEPROM

1 FB-Deterministic-DIV2 reset (here REG6_RB<2> == 0)

c Blocks

0 FB-Divider started with delay block (RC), normal operation

FB_START_BYPASS

1 FB-Divider can be started with external REF_SEL-signal (pin)

All Output Dividers

0 Output-Dividers started with delay block (RC), normal operation

DET_START_BYPASS

EEPROM

1 Output-Dividers can be started with external NRESET-signal (pin)

PH6ADJC0

Output 6

PH6ADJC1

PH6ADJC2

PH6ADJC3

Coarse phase adjust select for Output Divider 6

EEPROM

PH6ADJC4

PH6ADJC5

PH6ADJC6

OUT6DIVRSEL0

OUT6DIVRSEL1

OUT6DIVRSEL2

Output Divider 6 ratio select

OUT6DIVRSEL3

Output 6

EEPROM

(seeTable 7)

OUT6DIVRSEL4

OUT6DIVRSEL5

OUT6DIVRSEL6

When set to 0, the divider is disabled

EN6DIV

Output 6

EEPROM

When set to 1, the divider is enabled

PECL6HISWING

Output 6

High Output Voltage Swing in LVPECL Mode if set to 1

EEPROM

CMOSMODE6PX

LVCMOS mode select for OUTPUT 6 Positive Pin.

Output 6

EEPROM

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

CMOSMODE6PY

CMOSMODE6NX

LVCMOS mode select for OUTPUT 6 Negative Pin.

Output 6

EEPROM

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

CMOSMODE6NY

RAM BITS

OUTPUT TYPE

OUTBUFSEL6X

Output 6

EEPROM

LVPECL

LVDS

OUTBUFSEL6Y

Output 6

LVCMOS

See Settings Above(1)

EEPROM

All Outputs Disabled

(1)

Use description for bits 22,23,24, and 25 for setting the LVCMOS outputs

Submit Documentation Feedback

Product Folder Link(s): CDCE72010

CDCE72010RGCT датащи(PDF) 27 Page - Texas Instruments

CDCE72010RGCT датащи(HTML) 27 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

датащи скачать

ссылки URL