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CDCE72010RGCT датащи(PDF) 48 Page - Texas Instruments

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номер детали CDCE72010RGCT
подробное описание детали  Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor
PDF  73 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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CDCE72010RGCT датащи(HTML) 48 Page - Texas Instruments

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INTERFACE, CONFIGURATION, AND CONTROL
RAMRegisters
EEPROMCells
Interface&Control
ControlSignals
SPI
UNIVERSAL INPUT AND REFERENCE CLOCK BUFFERS
50W
50W
PRI_REF
Input
50W
VBB
P
N
INV
50W
SEC_REF
Input
P
N
INV
--
--
--
--
ON
X
X
1
X
X
X
--
--
--
--
OFF
X
X
0
X
X
X
--
External
--
LVDS
ON
X
1
1
X
1
1
1.2V
Internal
DC
LVDS
ON
0
0
1
1
1
1
1.2V
Internal
AC
LVDS
ON
0
0
1
0
1
1
--
External
--
LVPECL
ON
X
1
1
X
0
1
1.2V
Internal
DC
LVPECL
ON
0
0
1
1
0
1
1.9V
Internal
AC
LVPECL
ON
0
0
1
0
0
1
--
N/A
DC
LVCMOS
ON
X
X
1
X
0
0
Vbb
Term
Coup
Mode
Hyst
1.3/4
1.2
1.1
1.0
0.1
0.0
Configuration
Settings
O
C
C
1
0
1
X
C
C
C
0
0
1
X
O
O
O
X
1
X
X
O
O
O
X
X
0
0
INV
N
P
1.3
1.2
0.1
0.0
Register / Bits
Switch
O
C
C
1
0
1
X
C
C
C
0
0
1
X
O
O
O
X
1
X
X
O
O
O
X
X
0
0
INV
N
P
1.4
1.2
0.1
0.0
Register / Bits
Switch
PRI_REF & SEC_REF Input Buffer Settings
PRI_REF Buffer Settings
SEC_REF Buffer Settings
CDCE72010
SCAS858A – JUNE 2008 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
The CDCE72010 is designed to support various applications with SPI bus interface and without. In the case
where systems lack the SPI bus or a Boot up configuration is required at start up before the management layer is
up the built in EEPROM is used to provide this function.
The Interface bus takes the serialized address and data and writes to the specified RAM bits. The content of the
RAM bits are connected to logical functions in the device. Changing the content of the RAM bits (high or low)
instantly changes the logical functions inside the device.
At power up or after power down is de-asserted the contents of the EEPROM bits are copied to their
corresponding RAM bits. After that the content of RAM can be changed via the SPI bus. When writing to
EEPROM commands are detected on the SPI bus the control logic begins writing the content of the RAM bits
into the corresponding EEPROM bits. This process takes about 50ms. During this time the power supply should
be above 3.2V.
The on-chip EEPROM can be operated in its unlocked or locked mode. An unlocked EEPROM indicates that the
stored bit values can be changed on another EEPROM write sequence (available for up to a 100 EEPROM write
sequences). A locked EEPROM indicates that the stored bit values cannot be changed on another EEPROM
write sequence.
Figure 15. Interface Control
The CDCE72010 is designed to support what is referred to as a Universal Input Buffer structure. This type of
buffer is designed to accept Differential or single ended inputs and it is sensitive enough to act as a LVPECL or
LVDS in differential mode and LVCMOS in Single ended mode. With the proper external termination various
types of inputs signals can be supported. Those inputs will be discussed in a separate document (application
Notes).
The CDCE72010 has two internal voltage biasing circuitries. One to set the termination voltage for references
(PRI_REF and SEC_REF) and the second biasing circuitry is to set the termination voltage to the VCXO_IN and
AUX_IN. This means that we can only have one type of differential signal on PRI_REF and SEC_REF and only
one type of differential signal on VCXO_IN and AUX_IN.
Figure 16. PRI_REF and SEC_REF Voltage Biasing Circuitry
48
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Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): CDCE72010



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