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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CDCE72010RGCT датащи(PDF) 49 Page - Texas Instruments |
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CDCE72010RGCT датащи(HTML) 49 Page - Texas Instruments |
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49 / 73 page  50W VCXO Input 50W VBB P N INV AUX Input -- -- -- -- ON X X 1 X X X -- -- -- -- OFF X X 0 X X X -- External -- LVDS ON X 1 1 X 1 1 1.2V Internal DC LVDS ON 0 0 1 1 1 1 1.2V Internal AC LVDS ON 0 0 1 0 1 1 -- External -- LVPECL ON X 1 1 X 0 1 1.2V Internal DC LVPECL ON 0 0 1 1 0 1 1.9V Internal AC LVPECL ON 0 0 1 0 0 1 -- N/A DC LVCMOS ON X X 1 X 0 0 Vbb Term Coup Mode Hyst 8.5 8.4 8.3 8.2 8.1 8.0 Configuration Settings O C C 1 0 1 X C C C 0 0 1 X O O O X 1 X X O O O X X 0 0 INV N P 8.5 8.4 8.1 8.0 Register / Bits Switch VCXO & AUX Input Buffer Settings VCXO Input Buffer Settings AUTOMATIC/MANUAL REFERENCE CLOCK SWITCHING (SMART MUX) PRI_REF SEC_REF Internal ReferenceClock VCXOWith 100HzLoop Auto-Reference 1 2 1 2 3 4 primary secondary primary CDCE72010 www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009 Figure 17. VCXO_IN and AUX_IN Voltage Biasing Circuitry The CDCE72010 supports two reference clock inputs, the primary clock input, PRI_REF, and the secondary clock input, SEC_REF. The clocks can be selected manually or automatically. The respective mode is selected by the dedicated SPI register. In the manual mode the external REF_SEL signal selects one of the two input clocks In the automatic mode the primary clock is selected by default even if both clocks are available. In case the primary clock is not available or fails, then the input switches to the secondary clock until the primary clock is back. The figure below shows the automatic clock selection. Figure 18. Automatic Clock Select Timing In the automatic mode the frequencies of both clock signals has to be similar but may differ by up to 20%. There is no limitation placed on the phase relationship between the two inputs. The clock input circuitry is designed to suppress glitches during switching between the primary and secondary clock in the manual and automatic mode. This insures that the clock outputs continue to clock reliably when a transition from a clock input occurs. The phase of the output clock will slowly follow the new input phase. The speed of this transition is determined by the loop bandwidth. However, there is no phase build-out function supported (like in SONET/SDH applications). Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 49 Product Folder Link(s): CDCE72010 |
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