CDCE72010RGCT datasheet(59/73 Pages) TI

59 / 73 page

OUTPUT DIVIDERS AND PHASE ADJUST

DDDDD

StartDivider

(OUT#DIVSEL#)

(PH#ADJC#)

OutputDivider

CoarsePhase AdjustSelect

Phase AdjustPeriod

CDCE72010

www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009

The CDCE72010 is designed with individual Output Dividers for Outputs 1 to 8. Output Divider 1 drives Output 1

and Output 0 and Output Divider 8 drives Output 8 and Output 9. Each output divider has a bypass function or it

is referred to as divide by “one”. Since divide by one bypasses the divider block it can address higher operating

frequencies.

The output divider is designed to address divide by 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 18, 20, 24, 28, 30, 32, 36, 40,

42, 48, 50, 56, 60, 64, 70 and 80.The output divider includes a coarse phase adjust that shifts the divided clock

signal. The phase adjust resolution is a function of the divide function. The maximum number of phase steps

equals to the divider setting.

If the output is divide by 2, then two phase adjustment settings (0 and 180 degrees) are available. The resolution

of phase adjustment is related to the output divider setting by the following: Phase adjust resolution = (1/Output

Divider settings) X 360 Degrees.

Example: For a 491.52MHz VCXO where one of the outputs of the device is set to divide by 16 for a 30.72MHz

desired output, this will mean that the 30.72MHz clock will have (1/16) X 360 = 22.5 Degrees of phase

adjustment resolution.

Output Divide Select (OUT#DIVSEL#) and Coarse Phase Adjust Select (PH#ADJC#) registers are located in

The Phase difference between 2 divider settings on different output can be calculated using the following formula

and referring to the Phase Lag number in the Output Divider Table ( see Table 7).

Integer Remainder of [(Phase Lag X - Phase Lag Y)/ Divide X ] as an example if we need to calculate the phase

difference between divide by 4 and divide by 8 with respect to divide by 4 clock.

The Integer Remainder [(28.5 - 0.5)/4] = 0. This means there is 0 Cycle phase delay between Divide by 4 and

Divide by 8 with respect to Divide by 4 Clock.

If we need to do the same calculation with respect to Divide by 8 we will have Intger Remainder [(28.5 – 0.5)/8] =

0.5 that means that there is 0.5 Cycles between Divide by 4 and divide by 8 with respect to a divide by 8 clock.

Figure 25. Maximum Output Frequency With Phase Alighment

For a complete listing of the coarse phase adjust settings, refer to the "CDCE72010 Coarse Phase Adjust"

document.

Submit Documentation Feedback

Product Folder Link(s): CDCE72010

CDCE72010RGCT датащи(PDF) 59 Page - Texas Instruments

CDCE72010RGCT датащи(HTML) 59 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

датащи скачать

ссылки URL