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CDCE72010RGCT датащи(PDF) 52 Page - Texas Instruments

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номер детали CDCE72010RGCT
подробное описание детали  Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor
PDF  73 Pages
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CDCE72010RGCT датащи(HTML) 52 Page - Texas Instruments

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PHASE DELAY FOR M AND N
Delay Block in M/N Path
CDCE72010
SCAS858A – JUNE 2008 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
Table 11. Reference Delay M (PRI_REF or SEC_REF) and Feedback Delay N (VCXO) Phase Adjustment
(Register 2 RAM Bits [5:0]) (1)
DLYM2/DLYN2
DLYM1/DLYN1
DLYM0/DLYN0
PHASE OFFSET
0
0
0
0ps(2)
0
0
1
±160ps
0
1
0
±320ps
0
1
1
±480ps
1
0
0
±830ps
1
0
1
±1130ps
1
1
0
±1450ps
1
1
1
±1750ps
(1)
If Progr Delay M is set, all Yx outputs are lagging to the Reference Clock according to the value set. If Progr Delay N is set, all Yx
outputs are leading to the Reference Clock according to the value set. Above are typical values at VCC = 3.3 V, TA = 25°C, PECL-output
relate to Div4 mode.
(2)
Default
Table 12. Reference Divider M/N 14-Bit (Register 10 RAM Bits [13:0] for M and RAM Bits [27:14] for N)
N13
N12
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
DIV BY(1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
0
0
0
0
0
0
0
0
0
0
0
0
1
0
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
•
•
•
0
0
0
0
0
0
0
1
1
1
1
1
1
1
128(2)
•
•
•
1
1
1
1
1
1
1
1
1
1
1
1
0
1
16382
1
1
1
1
1
1
1
1
1
1
1
1
1
0
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
16384
(1)
If the divider value is Q, then the code will be the binary value of (Q - 1).
(2)
Default
52
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