CDCE72010RGCT datasheet(64/73 Pages) TI

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Output Dividers Synchronization

Reference Clock

REG0<Bit4> VCXOSEL

“1”

“0” REG6<Bit5>

DET_START_BYPASS

REG6<Bit2> FB_DETERM_DIV_SEL

“0” Feedback Divider Clock

“1” Divide by 2 Feedback Clock

Any of the Conditions will Produce a Conditional SYNC Start Signal:

1- REG9 <Bit11> INDET_BP is set to “0” & VCXO or AUX_CLK is available

2- REG9<Bit12> PLL_LOCK_BP is set to “0” & we have 1st Lock State

3- REG11<Bit19> PD_PLL is set to “0”& the PLL is ON

4- REG9<Bit13> LOW_FD_FB_EN is set to “1” N Divider Input Frequency above 600KHz

5- Write Activity to the Output Divider (s)

6- REG12<Bit8> Set to 1 ( /RESET Bit is Set to “1”)

7- REG12<Bit7> Set to 1 ( /Power Down Bit is Set to “1”)

/RESET Pin

“0”

1” REG9<Bit10>

STARTBYPASS

Feedback Clock

“0”

“1”

OUTPUT DIVIDERS

SYNC SIGNAL

Synchronizing Output Divider SYNC Signal

If the value of the bits described as inverted the function associated with it will be ignored

with respect to the sync start signal generation.

CDCE72010

SCAS858A – JUNE 2008 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com

The CDCE72010 is a 10 output clock device with 8 output dividers and to insure that all the outputs are

synchronous a synchronization startup circuitry is used. The synchronization circuitry generates a pulse to reset

all the dividers in a way, that a predictable synchronous output is generated. The Synchronization signal can be

generated from different sources and can be synchronized to a specific clock. The Block diagram below

illustrates the signal path of the Output Divider Sync Signal. This function is assured up to 500 MHz.

NOTE:

The minimum frequency required for the output synchronization block to work properly

is 1 MHz.

Figure 30. Output Divider Synchronization Block Diagram

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