P89LPC9331FDH datasheet(64/93 Pages) NXP

64 / 93 page

P89LPC9331_9341_9351_9361_3

Product data sheet

Rev. 03 — 2 June 2009

64 of 93

NXP Semiconductors

P89LPC9331/9341/9351/9361

8-bit microcontroller with accelerated two-clock 80C51 core

An early detection mechanism exists when the interrupt criteria has been selected to be

outside the boundary limits. In this case, after the four MSBs have been converted, these

four bits are compared with the four MSBs of the boundary high and low registers. If the

four MSBs of the conversion meet the interrupt criteria (i.e., outside the boundary limits)

an interrupt will be generated, if enabled. If the four MSBs do not meet the interrupt

criteria, the boundary limits will again be compared after all 8 bits have been converted.

The boundary status register (BNDSTA0) ﬂags the channels which caused a boundary

interrupt.

8.9 DAC output to a port pin with high output impedance

Each ADC’s DAC block can be output to a port pin. In this mode, the ADxDAT3 register is

used to hold the value fed to the DAC. After a value has been written to the DAC (written to

ADxDAT3), the DAC output will appear on the channel 3 pin.

8.10 Clock divider

The ADC requires that its internal clock source be in the range of 320 kHz to 8 MHz to

maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is

provided for this purpose.

8.11 Power-down and Idle mode

In Idle mode the ADC, if enabled, will continue to function and can cause the device to exit

Idle mode when the conversion is completed if the A/D interrupt is enabled. In

Power-down mode or Total Power-down mode, the A/D, PGA and temperature sensor do

not function. If the PGAs, temperature sensor or the A/D are enabled, they will consume

power. Power can be reduced by disabling the PGA, temperature sensor and A/D.

P89LPC9331FDH датащи(PDF) 64 Page - NXP Semiconductors