P89LPC9331FDH datasheet(54/93 Pages) NXP

54 / 93 page

P89LPC9331_9341_9351_9361_3

Product data sheet

Rev. 03 — 2 June 2009

54 of 93

NXP Semiconductors

P89LPC9331/9341/9351/9361

8-bit microcontroller with accelerated two-clock 80C51 core

7.28 Watchdog timer

The watchdog timer causes a system reset when it underﬂows as a result of a failure to

feed the timer prior to the timer reaching its terminal count. It consists of a programmable

12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap

taken from the prescaler. The clock source for the prescaler can be the PCLK, the nominal

400 kHz watchdog oscillator or crystal oscillator. The watchdog timer can only be reset by

a power-on reset. When the watchdog feature is disabled, it can be used as an interval

timer and may generate an interrupt. Figure 22 shows the watchdog timer in Watchdog

mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the

watchdog clock and the CPU is powered down, the watchdog is disabled. The watchdog

timer has a time-out period that ranges from a few

µs to a few seconds. Please refer to the

P89LPC9331/9341/9351/9361

User manual for more details.

7.29 Additional features

7.29.1 Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,

as if an external reset or watchdog reset had occurred. Care should be taken when writing

to AUXR1 to avoid accidental software resets.

7.29.2 Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address

used with certain instructions. The DPS bit in the AUXR1 register selects one of the two

Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may

be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,

without the possibility of inadvertently altering other bits in the register.

(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed

sequence.

Fig 22. Watchdog timer in Watchdog mode (WDTE = 1)

PRE2

PRE1

PRE0

WDRUN

WDTOF

WDCLK

WDCON (A7H)

SHADOW REGISTER

PRESCALER

002aae015

8-BIT DOWN

COUNTER

WDL (C1H)

watchdog

oscillator

crystal

oscillator

PCLK

XTALWD

÷32

MOV WFEED1, #0A5H

MOV WFEED2, #05AH

reset(1)

P89LPC9331FDH датащи(PDF) 54 Page - NXP Semiconductors

P89LPC9331FDH датащи(HTML) 54 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

датащи скачать

ссылки URL