P89LPC9331FDH datasheet(41/93 Pages) NXP

41 / 93 page

P89LPC9331_9341_9351_9361_3

Product data sheet

Rev. 03 — 2 June 2009

41 of 93

NXP Semiconductors

P89LPC9331/9341/9351/9361

8-bit microcontroller with accelerated two-clock 80C51 core

7.20.6 Timer overﬂow toggle output

Timers 0 and 1 can be conﬁgured to automatically toggle a port output whenever a timer

overﬂow occurs. The same device pins that are used for the T0 and T1 count inputs are

also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the ﬁrst

timer overﬂow when this mode is turned on.

7.21 RTC/system timer

The P89LPC9331/9341/9351/9361 has a simple RTC that allows a user to continue

running an accurate timer while the rest of the device is powered down. The RTC can be a

wake-up or an interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit

prescaler and a 16-bit loadable down counter. When it reaches all logic 0s, the counter will

be reloaded again and the RTCF ﬂag will be set. The clock source for this counter can be

either the CPU clock (CCLK) or the XTAL oscillator. Only power-on reset and watchdog

reset will reset the RTC and its associated SFRs to the default state.

The 16-bit loadable counter portion of the RTC is readable by reading the RTCDATL and

RTCDATH registers.

7.22 CCU (P89LPC9351/9361)

This unit features:

• A 16-bit timer with 16-bit reload on overﬂow.

• Selectable clock, with prescaler to divide clock source by any integral number

between 1 and 1024.

• Four compare/PWM outputs with selectable polarity

• Symmetrical/asymmetrical PWM selection

• Two capture inputs with event counter and digital noise rejection ﬁlter

• Seven interrupts with common interrupt vector (one overﬂow, two capture, four

compare)

• Safe 16-bit read/write via shadow registers.

7.22.1 CCU clock

The CCU runs on the CCUCLK, which is either PCLK in basic timer mode, or the output of

a PLL. The PLL is designed to use a clock source between 0.5 MHz to 1 MHz that is

multiplied by 32 to produce a CCUCLK between 16 MHz and 32 MHz in PWM mode

(asymmetrical or symmetrical). The PLL contains a 4-bit divider to help divide PCLK into a

frequency between 0.5 MHz and 1 MHz.

7.22.2 CCUCLK prescaling

This CCUCLK can further be divided down by a prescaler. The prescaler is implemented

as a 10-bit free-running counter with programmable reload at overﬂow.

7.22.3 Basic timer operation

The timer is a free-running up/down counter with a direction control bit. If the timer

counting direction is changed while the counter is running, the count sequence will be

reversed. The timer can be written or read at any time.

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