P89LPC9331FDH datasheet(57/93 Pages) NXP

57 / 93 page

P89LPC9331_9341_9351_9361_3

Product data sheet

Rev. 03 — 2 June 2009

57 of 93

NXP Semiconductors

P89LPC9331/9341/9351/9361

8-bit microcontroller with accelerated two-clock 80C51 core

without additional components. Two methods are available to accomplish IAP. A set of

predeﬁned IAP functions are provided in a Boot ROM and can be called through a

common interface, PGM_MTP. Several IAP calls are available for use by an application

program to permit selective erasing and programming of ﬂash sectors, pages, security

bits, conﬁguration bytes, and device ID. These functions are selected by setting up the

microcontroller’s registers before making a call to PGM_MTP at FF03H. The Boot ROM

occupies the program memory space at the top of the address space from FF00H to

FEFFH, thereby not conﬂicting with the user program memory space.

In addition, IAP operations can be accomplished through the use of four SFRs consisting

of a control/status register, a data register, and two address registers. Additional details

may be found in the P89LPC9331/9341/9351/9361

User manual.

7.30.8 ISP

ISP is performed without removing the microcontroller from the system. The ISP facility

consists of a series of internal hardware resources coupled with internal ﬁrmware to

facilitate remote programming of the P89LPC9331/9341/9351/9361 through the serial

port. This ﬁrmware is provided by NXP and embedded within each

P89LPC9331/9341/9351/9361 device. The NXP ISP facility has made in-system

programming in an embedded application possible with a minimum of additional expense

in components and circuit board area. The ISP function uses ﬁve pins (VDD, VSS, TXD,

RXD, and RST). Only a small connector needs to be available to interface your application

to an external circuit in order to use this feature.

7.30.9 Power-on reset code execution

The P89LPC9331/9341/9351/9361 contains two special ﬂash elements: the Boot Vector

and the Boot Status bit. Following reset, the P89LPC9331/9341/9351/9361 examines the

contents of the Boot Status bit. If the Boot Status bit is set to zero, power-up execution

starts at location 0000H, which is the normal start address of the user’s application code.

When the Boot Status bit is set to a value other than zero, the contents of the Boot Vector

are used as the high byte of the execution address and the low byte is set to 00H.

Table 10 shows the factory default Boot Vector setting for these devices. A

factory-provided bootloader is pre-programmed into the address space indicated and

uses the indicated bootloader entry point to perform ISP functions. This code can be

erased by the user.

Remark: Users who wish to use this loader should take precautions to avoid erasing the

1 kB sector that contains this bootloader. Instead, the page erase function can be used to

erase the ﬁrst eight 64-byte pages located in this sector.

A custom bootloader can be written with the Boot Vector set to the custom bootloader, if

desired.

Table 10.

Default boot vector values and ISP entry points

Device

Default

boot vector

Default

bootloader

entry point

Default bootloader

code range

1 kB sector

range

P89LPC9331

0FH

0F00H

0E00H to 0FFFH

0C00H to 0FFFH

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