P89LPC9331FDH datasheet(19/93 Pages) NXP

номер детали	P89LPC9331FDH

подробное описание детали	8-bit microcontroller with accelerated two-clock 80C51 core, 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCs

PDF	93 Pages

Scroll/Zoom	100%

производитель	NXP [NXP Semiconductors]

домашняя страница	http://www.nxp.com

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19 / 93 page

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[1]

All ports are in input only (high-impedance) state after power-up.

[2]

BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.

[3]

The RSTSRC register reﬂects the cause of the P89LPC9331/9341 reset except BOIF bit. Upon a power-up reset, all reset source ﬂags are cleared except POF and BOF; the

power-on reset value is x011 0000.

[4]

After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.

Other resets will not affect WDTOF.

[5]

On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6]

The only reset sources that affect these SFRs are power-on reset and watchdog reset.

WDL

Watchdog load

C1H

1111 1111

WFEED1

Watchdog

feed 1

C2H

WFEED2

Watchdog

feed 2

C3H

Table 4.

Special function registers - P89LPC9331/9341 …continued

* indicates SFRs that are bit addressable.

Name

Description

SFR

addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

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