P89LPC9331FDH datasheet(56/93 Pages) NXP

56 / 93 page

P89LPC9331_9341_9351_9361_3

Product data sheet

Rev. 03 — 2 June 2009

56 of 93

NXP Semiconductors

P89LPC9331/9341/9351/9361

8-bit microcontroller with accelerated two-clock 80C51 core

• Programmable security for the code in the ﬂash for each sector.

• 100,000 typical erase/program cycles for each byte.

• 10 year minimum data retention.

7.30.3 Flash organization

The program memory consists of sixteen 1 kB sectors on the P89LPC9361 devices and

eight 1 kB sectors on the P89LPC9341/9351 devices and four 1 kB sectors on the

P89LPC9331 device. Each sector can be further divided into 64-byte pages. In addition to

sector erase, page erase, and byte erase, a 64-byte page register is included which allows

from 1 byte to 64 bytes of a given page to be programmed at the same time, substantially

reducing overall programming time.

7.30.4 Using ﬂash as data storage

The ﬂash code memory array of this device supports individual byte erasing and

programming. Any byte in the code memory array may be read using the MOVC

instruction, provided that the sector containing the byte has not been secured (a MOVC

instruction is not allowed to read code memory contents of a secured sector). Thus any

byte in a non-secured sector may be used for non-volatile data storage.

7.30.5 Flash programming and erasing

Four different methods of erasing or programming of the ﬂash are available. The ﬂash may

be programmed or erased in the end-user application (IAP) under control of the

application’s ﬁrmware. Another option is to use the ICP mechanism. This ICP system

provides for programming through a serial clock/serial data interface. As shipped from the

factory, the upper 512 bytes of user code space contains a serial ISP routine allowing for

the device to be programmed in circuit through the serial port. The ﬂash may also be

programmed or erased using a commercially available EPROM programmer which

supports this device. This device does not provide for direct veriﬁcation of code memory

contents. Instead, this device provides a 32-bit CRC result on either a sector or the entire

user code space.

Remark: When voltage supply is lower than 2.4 V, the BOD FLASH is tripped and ﬂash

erase/program is blocked.

7.30.6 ICP

ICP is performed without removing the microcontroller from the system. The ICP facility

consists of internal hardware resources to facilitate remote programming of the

P89LPC9331/9341/9351/9361 through a two-wire serial interface. The NXP ICP facility

has made in-circuit programming in an embedded application - using commercially

available programmers - possible with a minimum of additional expense in components

and circuit board area. The ICP function uses ﬁve pins. Only a small connector needs to

be available to interface your application to a commercial programmer in order to use this

feature. Additional details may be found in the P89LPC9331/9341/9351/9361

User

manual.

7.30.7 IAP

IAP is performed in the application under the control of the microcontroller’s ﬁrmware. The

IAP facility consists of internal hardware resources to facilitate programming and erasing.

The NXP IAP has made in-application programming in an embedded application possible

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