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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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P89LPC9331FDH датащи(PDF) 43 Page - NXP Semiconductors |
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P89LPC9331FDH датащи(HTML) 43 Page - NXP Semiconductors |
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43 / 93 page  P89LPC9331_9341_9351_9361_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 2 June 2009 43 of 93 NXP Semiconductors P89LPC9331/9341/9351/9361 8-bit microcontroller with accelerated two-clock 80C51 core 7.22.7 Alternating output mode In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating pairs for bridge drive control. In this mode the output of these PWM channels are alternately gated on every counter cycle. 7.22.8 PLL operation The PWM module features a Phase Locked Loop that can be used to generate a CCUCLK frequency between 16 MHz and 32 MHz. At this frequency the PWM module provides ultrasonic PWM frequency with 10-bit resolution provided that the crystal frequency is 1 MHz or higher. The PLL is fed an input signal from 0.5 MHz to 1 MHz and generates an output signal of 32 times the input frequency. This signal is used to clock the timer. The user will have to set a divider that scales PCLK by a factor from 1 to 16. This divider is found in the SFR register TCR21. The PLL frequency can be expressed as shown in Equation 1: (1) Where: N is the value of PLLDV3:0. Fig 10. Symmetrical PWM TOR2 compare value timer value non-inverted inverted 002aaa894 0 Fig 11. Alternate output mode TIMER VALUE 002aaa895 0 TOR2 COMPARE VALUE A (or C) COMPARE VALUE B (or D) PWM OUTPUT (OCA or OCC) PWM OUTPUT (OCB or OCD) PLL frequency PCLK N1 + () ------------------ = |
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