P89LPC9331FDH datasheet(55/93 Pages) NXP

55 / 93 page

P89LPC9331_9341_9351_9361_3

Product data sheet

Rev. 03 — 2 June 2009

55 of 93

NXP Semiconductors

P89LPC9331/9341/9351/9361

8-bit microcontroller with accelerated two-clock 80C51 core

7.29.3 Data EEPROM (P89LPC9351/9361)

The P89LPC9351/9361 has 512 bytes of on-chip Data EEPROM. The Data EEPROM is

SFR based, byte readable, byte writable, and erasable (via row ﬁll and sector ﬁll). The

user can read, write and ﬁll the memory via SFRs and one interrupt. This Data EEPROM

provides 100,000 minimum erase/program cycles for each byte.

• Byte mode: In this mode, data can be read and written one byte at a time.

• Row ﬁll: In this mode, the addressed row (64 bytes) is ﬁlled with a single value. The

entire row can be erased by writing 00H.

• Sector ﬁll: In this mode, all 512 bytes are ﬁlled with a single value. The entire sector

can be erased by writing 00H.

After the operation ﬁnishes, the hardware will set the EEIF bit, which if enabled will

generate an interrupt. The ﬂag is cleared by software.

Remark: When voltage supply is lower than 2.4 V, the BOD EEPROM is tripped and Data

EEPROM program or erase is blocked. EWERR1 and EWERR0 bits are used to indicate

the write error for BOD EEPROM. Both can be cleared by power-on reset, watchdog reset

or software write.

7.30 Flash program memory

7.30.1 General description

The P89LPC9331/9341/9351/9361 ﬂash memory provides in-circuit electrical erasure and

programming. The ﬂash can be erased, read, and written as bytes. The Sector and Page

Erase functions can erase any ﬂash sector (1 kB) or page (64 bytes). The Chip Erase

operation will erase the entire program memory. ICP using standard commercial

programmers is available. In addition, IAP and byte-erase allows code memory to be used

for non-volatile data storage. On-chip erase and write timing generation contribute to a

user-friendly programming interface. The P89LPC9331/9341/9351/9361 ﬂash reliably

stores memory contents even after 100,000 erase and program cycles. The cell is

designed to optimize the erase and programming mechanisms. The

P89LPC9331/9341/9351/9361 uses VDD as the supply voltage to perform the

Program/Erase algorithms. When voltage supply is lower than 2.4 V, the BOD FLASH is

tripped and ﬂash erase/program is blocked.

7.30.2 Features

• Programming and erase over the full operating voltage range.

• Byte erase allows code memory to be used for data storage.

• Read/Programming/Erase using ISP/IAP/ICP.

• Internal ﬁxed boot ROM, containing low-level IAP routines available to user code.

• Default loader providing ISP via the serial port, located in upper end of user program

memory.

• Boot vector allows user-provided ﬂash loader code to reside anywhere in the ﬂash

memory space, providing ﬂexibility to the user.

• Any ﬂash program/erase operation in 2 ms.

• Programming with industry-standard commercial programmers.

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