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P89LPC970FDH датащи(PDF) 57 Page - NXP Semiconductors |
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P89LPC970FDH датащи(HTML) 57 Page - NXP Semiconductors |
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57 / 66 page ![]() P89LPC97X_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 27 April 2010 57 of 66 NXP Semiconductors P89LPC970/971/972 8-bit microcontroller with accelerated two-clock 80C51 core 10.2 ISP entry mode Fig 22. SPI slave timing (CPHA = 1) 002aaa911 TSPICYC tSPICLKH tSPICLKH tSPICLKL tSPILEAD tSPICLKL tSPILAG tSPIDSU tSPIDSU tSPIDH tSPIDH tSPIF tSPIR tSPIR tSPIA tSPIOH tSPIOH tSPIOH tSPIDIS slave MSB/LSB out not defined MSB/LSB in LSB/MSB in slave LSB/MSB out tSPIDV tSPIDV tSPIDV tSPIR tSPIF tSPIF SS SPICLK (CPOL = 0) (input) SPICLK (CPOL = 1) (input) MISO (output) MOSI (input) Table 14. Dynamic characteristics, ISP entry mode VDD = 2.4 V to 5.5 V, unless otherwise specified. Tamb = −40 °Cto+85 °C for industrial applications, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit tVR VDD active to RST active delay time pin P1.5/RST 50 - - μs tRH RST HIGH time pin P1.5/RST 1- 32 μs tRL RST LOW time pin P1.5/RST 1- - μs Fig 23. ISP entry waveform 002aaa912 VDD RST tRL tVR tRH |
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