P89LPC970FDH datasheet(31/66 Pages) NXP

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P89LPC97X_2

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Product data sheet

Rev. 02 — 27 April 2010

31 of 66

NXP Semiconductors

P89LPC970/971/972

8-bit microcontroller with accelerated two-clock 80C51 core

7.20.1 Mode 0: 16-bit timer/counter with auto-reload

Mode 0 configures the timer register as an 16-bit Timer/counter with automatic reload. An

overflow upon the timer or a 1-to-0 transition at TxEX pin can cause the reload event.

7.20.2 Mode 1: 16-bit timer/counter with input capture

Mode 1 configures the timer register as an 16-bit Timer/counter with input capture. A

1-to-0 transition at TxEX pin can cause the capture event.

7.20.3 Mode 2: 16-bit PWM mode

In this mode, the corresponding timer can be changed to a 16-bit PWM generator with

adjustable duty cycle. In this mode, the corresponding timer can be changed to a 16-bit

PWM generator with adjustable duty cycle and adjustable full period (from 0, theoretically,

to 131072).

7.20.4 Timer overflow toggle output

Timers 2, 3 and 4 can be configured to automatically toggle a port output whenever a

timer overflow occurs. The same device pins that are used for the T2, T3 and T4 count

inputs are also used for the timer toggle outputs. The port outputs will be a logic 1 prior to

the first timer overflow when this mode is turned on.

7.21 RTC/system timer

The P89LPC970/971/972 has a simple RTC that allows a user to continue running an

accurate timer while the rest of the device is powered down. The RTC can be a wake-up

or an interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler

and a 16-bit loadable down counter. When it reaches all logic 0s, the counter will be

reloaded again and the RTCF flag will be set. The clock source for this counter can be

either the CPU clock (CCLK) or the XTAL oscillator. Only power-on reset and watchdog

reset will reset the RTC and its associated SFRs to the default state.

The 16-bit loadable counter portion of the RTC is readable by reading the RTCDATL and

RTCDATH registers.

7.22 UART

The P89LPC970/971/972 has an enhanced UART that is compatible with the

conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate

source. The P89LPC970/971/972 does include an independent baud rate generator. The

baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or

the independent baud rate generator. In addition to the baud rate generation,

enhancements over the standard 80C51 UART include Framing Error detection,

automatic address recognition, selectable double buffering and several interrupt options.

The UART can be operated in four modes: shift register, 8-bit UART, 9-bit UART, and CPU

clock/32 or CPU clock/16.

7.22.1 Mode 0

Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are

transmitted or received, LSB first. The baud rate is fixed at 1

⁄

16 of the CPU clock

frequency.

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