P89LPC970FDH datasheet(36/66 Pages) NXP

36 / 66 page

P89LPC97X_2

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Product data sheet

Rev. 02 — 27 April 2010

36 of 66

NXP Semiconductors

P89LPC970/971/972

8-bit microcontroller with accelerated two-clock 80C51 core

7.24 SPI (Pin remap)

The P89LPC970/971/972 provides another high-speed serial communication interface:

the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with

two operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be supported in

either Master mode or Slave mode. It has a Transfer Completion Flag and Write Collision

Flag Protection.

The SPI interface has four pins: SPICLK, MOSI, MISO and SS:

• SPICLK, MOSI and MISO are typically tied together between two or more SPI

devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows

from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output

in the Master mode and is input in the Slave mode. If the SPI system is disabled, i.e.,

SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.

• SS is the optional slave select pin. In a typical configuration, an SPI master asserts

one of its port pins to select one SPI device as the current slave. An SPI slave device

uses its SS pin to determine whether it is selected.

Typical connections are shown in Figure 11 through Figure 13.

Fig 10. SPI block diagram

002aaf091

CPU clock

DIVIDER

BY 4, 16, 64, 128

SELECT

CLOCK LOGIC

SPI CONTROL REGISTER

READ DATA BUFFER

8-BIT SHIFT REGISTER

SPI CONTROL

SPI STATUS REGISTER

SPI clock (master)

CONTROL

LOGIC

MISO

P1.6

MOSI

P1.7

SPICLK

P0.0

P1.4

SPI

interrupt

request

internal

data

bus

MSTR

SPEN

clock

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