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[1]

BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.

[2]

All ports are in input only (high-impedance) state after power-up.

[3]

The RSTSRC register reflects the cause of the P89LPC970/971/972 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the

power-on reset value is x011 0000.

[4]

The only reset sources that affect these SFRs are power-on reset and watchdog reset.

[5]

On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6]

After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.

Other resets will not affect WDTOF.

TH4

Timer/Counter 4

high byte

CCH

00

0000 000

0

TL4

Timer/Counter 4

low byte

CBH

00

0000 0000

TINTF

Timer/Counters

2/3/4 overflow

and external

flags

CEH

-

-

TF4

EXF4

TF3

EXF3

TF2

EXF2

00

0000 000

0

TRIM

Internal

oscillator trim

register

96H

RCCLK

ENCLK

TRIM.5

TRIM.4

TRIM.3

TRIM.2

TRIM.1

TRIM.0

[4][5]

WDCON

Watchdog

control register

A7H

PRE2

PRE1

PRE0

-

-

WDRUN

WDTOF

WDCLK

[4][6]

WDL

Watchdog load

C1H

FF

1111 1111

WFEED1 Watchdog

feed 1

C2H

WFEED2 Watchdog

feed 2

C3H

Table 4.

* indicates SFRs that are bit addressable.

Name

Description

SFR

addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary