ATmega32A datasheet(43/352 Pages) ATMEL

43 / 352 page

8155B–AVR–07/09

ATmega32A

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and then reset

the MCUCSR as early as possible in the program. If the register is cleared before another reset

occurs, the source of the reset can be found by examining the Reset Flags.

10.5.2

WDTCR – Watchdog Timer Control Register

• Bits 7:5 – Res: Reserved Bits

These bits are reserved bits in the ATmega32A and will always read as zero.

• Bit 4 – WDTOE: Watchdog Turn-off Enable

This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not

be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the

description of the WDE bit for a Watchdog disable procedure.

• Bit 3 – WDE: Watchdog Enable

When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written

to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE

bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be

followed:

In the same operation, write a logic one to WDTOE and WDE. A logic one must be writ-

ten to WDE even though it is set to one before the disable operation starts.

Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.

• Bits 2:0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0

Bit

765

210

–

WDTOE

WDE

WDP2

WDP1

WDP0

WDTCR

Read/Write

R/W

Initial Value

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